# Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley.

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Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

Summary of last lecture NMOS transistor PMOS transistor

Summary of transistor ideal (Shockley) model for nMOS for pMOS

DC transfer characteristics

PMOS on (linear), NMOS off Vin = 0

PMOS on (linear), NMOS on (saturation) V in = 0.2V DD

PMOS on (linear ~ sat) and NMOS (sat) V in = 0.4V DD

PMOS on (sat) NMOS on (linear) Vin = 0.6VDD

PMOS on (off ~ linear) and NMOS on (linear) Vin = 0.8VDD

NMOS on (linear) and PMOS cut off Vin = VDD

Summary of voltage transfer function A B C E D

Noise margins

CMOS inverter noise margins desired regions of operation

What is the impact of altering the PMOS width in comparison to the NMOS width on the DC char? V in3 I dsn, |I dsp | V out V DD V in3 V V If we increase (decrease) the width of PMOS compared to NMOS  for the same input voltage, a higher (lower) output voltage is obtained V in V out

Impact of skewing transistor sizes on inverter noise margins  Increasing (decreasing) PMOS width to NMOS width increases (decreases) the low noise margin and decreases (increases) the high noise margin

Pass transistor DC characteristics  As the source can rise to within a threshold voltage of the gate, the output of several transistors in series is no more degraded than that of a single transistor

Summary Today –Covered DC transfer characteristics Next time –Transistor non-ideal behaviour

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