1. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 3 ASIC Library Design Application-Specific Integrated Circuits Michael John Sebastian Smith Addison Wesley, 1997

2. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 ASIC Library Design ASIC design is usually performed using a predefined and precharacterized library of cells In designing this library, the original designer had to optimize speed and area without knowing the actual application that the cells will be used for - i.e., how large a load they will be driving wire load fanout load Being aware of the source and effect of these trade-offs will make it easier to understand how to optimally design using the library cells

3. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Model of CMOS Inverter with Parasitic Resistances and Capacitances Figure 3.1A model for CMOS logic delay. (a) A CMOS inverter with load capacitance. (b) Input and output waveforms showing the definition of falling propagation delay t PDF. (c) The switch model of the inverter showing parasitic resistances and capacitances.

4. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Effect of Load Capacitance on Inverter Performance Figure 3.3Simulation of an inverter driving a variable number of gates on its output

5. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Parasitic Capacitances of a CMOS Transistor Figure 3.4Transistor parasitic capacitance. (a) An N- channel MOS transistor with gate length L and width W. (b) The components of the gate capacitance. (c) Approximating capacitances with planar components. (d) The components of the diffusion capacitance. (e)-(h) The dimensions of the gate, overlap, and sidewall capacitances.

6. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 V DD V V out V V in = V DD V in = 0 R Non R Pon V OH = V DD V OL = 0 V M = R Pon ) f(R Non, CMOS Inverter: Steady State Response R Non  1/W N R Pon  1/W P Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996

7. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 CMOS Inverter VTC Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996

8. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 The Ideal Gate V m = V dd /2 Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996

9. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Balanced CMOS Inverter Assume that due to differences in  p and  n, for a minimum sized transistor, R p = 2R n For a balanced inverter we want R P = R N, so in this case, W P must be 2W N W P /L P = 2/1 W N /L N = 2/1

10. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Logical Effort Figure 3.8Logical effort. (a) The input capacitance looking into the input capacitance of a minimum size inverter. (b) Sizing a logic cell’s transistors to have the same delay as a minimum size inverter. (c) The logical effort of a cell is C in /C inv.

11. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Logical Effort Of a Complex Gate Figure 3.10 An AOI221 cell with logical effort vector g=(8/3, 8/3, 7/3).

12. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 The Basic Trade-off to other gates (fanout) buffer Which is faster?