VCC Hardware Production Status Production VCC Locations and Dispositions Location CERN OSU RICE Florida Total 50 23 1 75 Disposition In Per. Crate ? --- Test Setups 2 4+ Waiting for BGA Replacement 3 Testing/Repair/Burn-in 15 Ready to Ship Hardware Development Non-Restrictive board design. Even though we may not utilize or implement some VME64x capabilities, the board is designed to be compatible with almost all VME64x functionality. Sent to PC house last week. Most parts are on hand. Board Stuffing to take place next week. Firmware Development Will be developed in stages. RocketIOTM implementation has been previously tried and tested. Start with rudimentary A24 D16 VME master. This means unpacking GbE, buffering to the FIFO, transfer from FIFO to VME port, conform to timing requirements, fill a buffer with any read data, create packet, and send to GbE. Add other functionality, flexibility, configuration control, and robustness as progress is made. This includes other transfer modes, define command structure or custom protocol structure for local and VME commands, add mechanism for setting and saving particular configurations, saving a default configuration, develop handshaking to deal with reset or full buffers, add status and monitoring and error reporting, add modules for system timer, arbiter, interrupt handler, etc. All components have arrived and all boards are stuffed. Most of the boards currently being tested should be ready to ship by the end of this week. J. Gu EMU Meeting, CERN Sept. 18, 2006

Reported VCC Related Issues Ref. # Issue Cause Resolution 1 DMB EPROM load Sperious Bus Request when executing ‘DELAY’ command Vcore boosted (improved failure rate) ISE 8.202i (gone with new compile) 2 TMB-CFEB timing test Multiple DLink driver conflicts. Changes to ethreset 3 9TMBs-to-MPC test VME SYSCLK disabled (problem for MPC during Hard Resets) Changed power up configuration to enable SYSCLK 4 BERR/missing data Valid data flag not set Vcore boosted (problem gone) Vcore (1.5V +/- 5%) was out of tolerance due to Vdrop across inductor. Boosting Vcore solved issue 4 but only decreased the frequency of issue 1. Recompiling (with no logic changes) using ISE 8.202i appears to have ‘fixed’ issue 1 but other compile issues have arisen (still investigating). Issue 2 has not reoccurred and does not appear to be a VCC issue. Issue 3 was simply a user configuration setup issue. J. Gu EMU Meeting, CERN Sept. 18, 2006

VCC Items to be done Replace resistor for 1.5V regulator. Add 10 uF Tant. bypass caps for oscillators (these were omitted during original board assembly). Continue firmware development to provide packet acknowledgements and ethernet firmware downloading. J. Gu EMU Meeting, CERN Sept. 18, 2006