Presentation on theme: "PPIB and ODMB Status Report Rice University April 19, 2013."— Presentation transcript:
PPIB and ODMB Status Report Rice University April 19, 2013
Test Stand at Rice April 19, 2013 2 2 skewclear cables (10 m)Seven SCSI cables (1.8 m) (temporary) PPIB7 CFEBs
PPIB Tests April 19, 2013 3 ● Power (all 9 cables connected, clock and most other signals running): - Output of the ODMB: 3.28V (8 lines in two 10m cables) - Input of the PPIB: 2.92V Need a separate voltage regulator on ODMB board - Current: 730 mA (~2.5W) ● 40MHz clock distribution on the PPIB is not perfect (7 loads, long line). Partial solution: use one of the four SN74LVC244 buffer (+ two wires). Need a dedicated clock driver in the final design. ● Inverted INJPLS signal (mistake in the schematic and layout). Fixed with wires. ● Can see all the signals on CFEB receivers, but SCSI cables distort the signals (twisted pairs do not match our dif pairs). OK with 3m Fischer-Backus sample cable. ● JTAG test: can reliably read FPGA ChipID from DCFEB to ODMB through the PPIB
ODMB Tests April 19, 2013 4 ● All major parts on all 5 boards work as expected (power, FPGA/PROM access, QPLL, VME FPGA and VME discrete logic interfaces, System Monitor, PPIB copper interface) ● CCB interface initially didn’t work. Found IC37, IC39, IC43, IC41 to be GTL16612 instead of GTLP16612. Three of them (IC37, IC39, IC41) have been replaced on all boards. ● SNAP12 receiver work as expected (at least 8 channels out of 12; but this is because my transmitter is only 8-channel). The OT1 (80Mhz) and OT2 (125Mhz) optical transceivers need more work (firmware) ● Tried to load the FPGA with a.bit file via VME. The FPGA is stuck in such a state that neither CCB Hard Reset, not front panel push button helps. Only power cycle can bring FPGA back to normal state. Reproducible. Continue investigation in contact with Stan and Ben. ● All LVDS transmitters to PPIB are powered from 2.5V instead of 3.3V. ● BERR and SYSFAIL outputs to VME, even if disabled in firmware, somehow force the VCC to “Busy” state… T2 and T3 removed on all boards…now OK ● Not tested: LVMB interface; ODMB-to-TMB backplane interface
Board Status April 19, 2013 5 ● PPIB: - 15 boards fabricated - 2 bare boards at CERN - 7 boards fully assembled: #1 at Rice, #2 at OSU #3 at UCSB #4, #5, #6, #7 shipped to CERN on April 18 ● ODMB: #1 at OSU #2 at UCSB #3 at Rice #4 shipped to CERN on April 18 #5 shipped to CERN on April 18 Missing front panels and stiffeners… Users be careful!