1. CS501 Advanced Computer Architecture
Lecture 27
Dr.Noor Muhammad Sheikh

2. Review

3. Programmed I/O Driver for 32 character Input Devices

4. Assumptions
Device driver can handle input from 32 different character input devices, at once.
Each input device has its own data and control registers.
The control register has a Ready status bit in position 31
The data register can only be read and returns the character in bits 7..0.

5. Continued
The data and control register’s address begins at address FFFFF300H.
Thus the 32 devices occupy word address from FFFF300H to FFFFF3FCH.
The device driver will input and store a line of characters from each device.
Each line determinated by a carriage return.
The driver is capable of handling input from all 32 devices by polling.

6. Continued
“Polling is a process by which the device driver tests each device in some predetermine order of priority, to see if it has a character ready.”

7. Continued Input from each device is controlled by 2 words
The first contain a pointer into a buffer.
The second is Done flag.
If Done flag is 0 then the device is actively receiving characters.
If Done flag is -1, the device will be inactive.

8. Fig (jordan)

9. Interrupt Driven I/O

10. Program Flow Program Flow Key Board Interrupt Serial Port Interrupt

11. Types of Interrupts

12. Interrupt Service routine

13. Continued
Software interrupts are usually associated with the software.
A simple output operation in a multitasking system requires software interrupts to be generated.
Output is usually handled by interrupts so that it appears interactive and asynchronous.
Notification of other events, such as expiry of a software timer is also handled by software interrupts.

14. Software interrupts are also used with system calls.
When the operating system switches from user mod e to supervisor mode it does so through software interrupts.
Consider an example where a user program must delete a file.
The user program will be executing in the user mode
When it makes the specific system call to delete the file, a software interrupt will be generated.

15. This will cause the processor to halt its current activity and switch to supervisor mode.
Once in supervisor mode, the operating system will delete the file and then control will return to the user program.
In supervisor mode the operating system would decide if it could delete the specified file with out harmful.
It is important that the system switch to super visor mode at each system call.

16. It is a routine which is executed when an interrupt occurs.
Also known as Interrupt Service Routine (ISR)
Deals with low-level events in the hardware of a computer system like a tick of a real-time clock.

17. An interrupt once generated must be serviced through an interrupt service routine.
These routines are stored in the system memory ready for execution.
Once the interrupt is generated, the processor must branch to the location of the appropriate service routine to execute it.

18. Vectored and Non Vectored Interrupts

19. The branch address of the interrupt service routine is fixed.
The code for the ISR is loaded at fixed memory location.
Very easy to implement and not flexible at all.

20. The number of peripheral devices is fixed and may not be increased.
Once the interrupt is generated the processor queries each device.
The processor does this to find out which device generated the interrup.

21. Vectored Interrupt

22. Vector Interrupt
Used to specify the address of the interrupt service routine.
The ode for ISR can be loaded anywhere in the memory.
This approach is much more flexible.
Using vectored interrupts, multiple devices may share the same interrupt input line.
A process called daisy chaining is then used to locate the interrupting device.

23. Interrupt vector is a fixed size structure that stores the address of the first instruction of the ISR.

24. All of the interrupt vectors are stored in the memory in this table.
Interrupt Vector Table is loaded at the memory location 0 for the 8086/8088.

25. Interrupts in 8086/8088 are vector interrupts.
Interrupt vector is of 4 bytes to store IP and CS.
Interrupt vector table is loaded at address 0 of main memory.
There is provision of 256 interrupts.

26. The number of interrupt is the number of interrupt vector in the interrupt vector table.
Since size of each vector is 4 bytes.
Interrupt vector starts from address 0.
The address of interrupt vector can be calculated by simply multiplying the number by 4.

27. Interrupt Handling

28. Interrupt Latency

29. Summary

30. User Level I\O Software Device-Independent Operating System Software
Device Drivers
Interrupts Handlers
hardware

31. (Most Significant Byte)
In 8086/8080 machines the size of interrupt vector is 4bytes that holds IP and CS of ISR.
Code Segment
(Most Significant Byte)
(Least Significant Byte)
Instruction Pointer
(Most significant Byte)
a +3
a +2
a +1 a