1. Status of GbE Peripheral Crate Controller
Ben Bylsma
EMU meeting
Fermilab, October 29, 2004

2. Hardware Status Nov. 6, 2003 (ESR) Hardware Development Oct. 29, 2004
Non-Restrictive board design.
Sent to PC house last week.
Most parts are on hand.
Board Stuffing to take place next week.
Oct. 29, 2004
2 stuffed boards (p4, & p7)
Testing hardware as firmware is developed.
Only minor problems found that will be corrected on the next version.
Hardware Development
Non-Restrictive board design.
Even though we may not utilize or implement some VME64x capabilities, the board is designed to be compatible with almost all VME64x functionality.
Sent to PC house last week.
Most parts are on hand.
Board Stuffing to take place next week.
Firmware Development
Will be developed in stages.
RocketIOTM implementation has been previously tried and tested.
Start with rudimentary A24 D16 VME master.
This means unpacking GbE, buffering to the FIFO, transfer from FIFO to VME port, conform to timing requirements, fill a buffer with any read data, create packet,
and send to GbE.
Add other functionality, flexibility, configuration control, and robustness as progress is made.
This includes other transfer modes, define command structure or custom protocol structure for local and VME commands, add mechanism for setting and saving particular configurations, saving a default configuration, develop handshaking to deal with reset or full buffers, add status and monitoring and error reporting, add modules for system timer, arbiter, interrupt handler, etc.
B. Bylsma EMU Meeting, Fermilab Oct. 29, 2004

3. Firmware Status Nov. 6, 2003 (ESR) Firmware Development Oct. 29, 2004
Will be developed in stages.
RocketIOTM implementation has been previously tried and tested.
Start with rudimentary A24 D16 VME master.
Add other functionality, flexibility, configuration control, and robustness as progress is made.
Oct. 29, 2004
GbE: Written and tested but not polished.
Ext. FIFO: Written and tested and possibly final version
VME: Mostly written but untested.
Flash RAM: Unwritten.
Hardware Development
Non-Restrictive board design.
Even though we may not utilize or implement some VME64x capabilities, the board is designed to be compatible with almost all VME64x functionality.
Sent to PC house last week.
Most parts are on hand.
Board Stuffing to take place next week.
Firmware Development
Will be developed in stages.
RocketIOTM implementation has been previously tried and tested.
Start with rudimentary A24 D16 VME master.
This means unpacking GbE, buffering to the FIFO, transfer from FIFO to VME port, conform to timing requirements, fill a buffer with any read data, create packet,
and send to GbE.
Add other functionality, flexibility, configuration control, and robustness as progress is made.
This includes other transfer modes, define command structure or custom protocol structure for local and VME commands, add mechanism for setting and saving particular configurations, saving a default configuration, develop handshaking to deal with reset or full buffers, add status and monitoring and error reporting, add modules for system timer, arbiter, interrupt handler, etc.
B. Bylsma EMU Meeting, Fermilab Oct. 29, 2004

4. Firmware Development Gigabit Ethernet Interface: Fifo interface:
Written and extensively tested.
Have transferred billions of bytes of data and millions of packets error free using random size jumbo packets.
Rate is limited by the server/driver. Had to throttle back the packet sending.
But short burst of smaller packets work fine.
Handling of MAC addresses is working fine, but currently it’s own MAC address is “hard-wired”.
Fifo interface:
Current functionality gives control for all potential uses of the FIFO.
Probably is the final version.
B. Bylsma EMU Meeting, Fermilab Oct. 29, 2004

5. Firmware Development VME Interface:
Has 13 sub-modules (2 are upper level sub-modules).
The low level modules enforce all the VME timing rules.
Either written or not currently necessary.
Close to final version.
Upper level sub-modules are written but not supporting all features yet.
Flash Memory Interface (Storing configurations):
Have not started yet.
B. Bylsma EMU Meeting, Fermilab Oct. 29, 2004