1. TMB and RAT Status Report
Endcap Muon OSU
April 16, 2004
Yangheng Zheng
University of California, Los Angeles
TMB Status
RAT Status

2. Endcap Muon meeting@OSU
TMB2003A and RAT2003A
Replaces problematic PHOS4 fine delays with commercial DDD devices
ALCT and RPC inputs through RAT (Rpc Alct Transition) board
Rad-hard regulators used, 1.5v added for Virtex-2 core voltage
4 base boards produced and bench-tested
2 mezzanine boards with faster and larger FPGA’s (Xilinx Virtex-2 XC2V4000)
Endcap Muon
04/16/2004

3. Endcap Muon meeting@OSU
TMB2004A and RAT2004A
Layout problems were fixed.
Power section was changed to allow Spartan-3 mezz. card upgrade (1.2v core voltage).
Firmware was re-written to get around Xilinx problem with use of global clock buffer lines for user I/O.
Endcap Muon
04/16/2004

4. TMB/RAT Original Pre-Production Planning (last Emu meeting)
January plan:
Build 27 working sets (TMB-base, TMB-mezz, RAT) by May 1:
20 for two full crates and two spares at CERN, 1 bench test setup, 1 OSU test setup, 1 Rice test setup, 2 UF Track Finder cosmic ray test stand, 1 UC FAST site, 1 additional spare
Front panels: 20 without ALCT cable access (for CERN), 7 with ALCT cable access (for debugging)
Mezzanine boards:
Cost of XC2V4000’s prohibitive, so made 10 with XC2V3000’s (temporary measure, 85% full without RPC logic).
Planned for a Spartan-3 layout (proceeding) to save ~$500K.
Endcap Muon
04/16/2004

5. TMB/RAT Pre-Production Current Status
32 TMB boards are bench-tested
Assembly house did a good job, very few errors.
As a result, testing was done ahead of schedule.
Tooling for Z-pack connector installation works well.
Virtex-2 mezzanine layout has a few bugs:
Pull-up resistors on some lines, pairs of output pads need to use same clock.
Firmware work-arounds implemented.
TMB regulators for mezzanine core voltage somewhat questionable:
Large ripple appears if mezzanine card is not plugged in.
32 RAT modules were assembled.
1 finished bench testing.
31 are in final assembly.
No problems seen thus far.
Endcap Muon
04/16/2004

6. Endcap Muon meeting@OSU
RAT Status and Plans
ME1 case: RPC input from Link boards
Need feedback from data interchange tests with RPC Link boards (~June at CERN).
May want to move RPC connectors back a little (~1.5 cm).
Will need to decide ME1 RPC cables, routing, strain relief.
ME2, ME3, ME4 case: no RPC inputs foreseen
Current RAT boards are fine for ALCT inputs.
Endcap Muon
04/16/2004

7. Endcap Muon meeting@OSU
TMB & RAT Planning
10 TMB2004A and 2 TMB2003A are currently useable (limited by number of mezzanine cards).
2 TMB2004A are at UF for preparing for CERN test beam.
1 TMB2004A are kept for reference and development.
7 TMB2004A + 1 TMB2003A are at OSU for full-crate test.
1 TMB2003A are at UC FAST site for development.
Next steps:
Do a full-crate test for CCB and MPC internal tests (at Rice before beam test?).
Send 4 TMB2004A to CERN for the test beam, early-to-mid May.
Endcap Muon
04/16/2004

8. Mezzanine Card Full Production
Virtex-2 versus Spartan-3:
Spartan-3 not available until 4th quarter of 2004.
Virtex series price was reduced.
Advantages of Virtex-2 XC2V4000:
Almost twice as fast as Virtex-E
Plenty of logic cells and memory for additional firmware:
Sensible ordering of pattern qualities (a problem in test beam 2003)
RPC data handling
Enough memory cells for “deadtime-free” triggering (like ALCT)
Available now
New quote brings these within the TMB budget.
Go ahead to procure XC2V4000’s?
Slight tweak needed for Virtex-2 mezzanine layout:
I/O pads are grouped in pairs, each pair needs to use the same clock.
Will be handled by PNPI.
(Spartan-3 layout proceeding anyway, cheaper by promised factor of ~2 than Virtex-II.)
Endcap Muon
04/16/2004

9. TMB2004A Cosmic Ray Testing
UF tests early April:
Only minor software changes needed to make TMB2004A work, but…
Have to rip apart system to do timing:
CFEB_Control needed in order to have modes to do timing and debugging.
CFEB_Control was incompatible with new CCB module.
When LCTs timed in, CFEB data was out-of-time:
Still need OSU experts to finish timing-in process.
Minor: event display data unpacking “broken” by 2-word status words addition to DDU output.
Continued development going on at UF, Rice, and UCLA FAST site:
UF?
Rice?
UCLA FAST?
Endcap Muon
04/16/2004

10. Test Beam Plans from TMB/RAT Perspective
Personnel:
Yangheng Zheng has been debugging the setup at UF and UC FAST sites.
Martin von der Mey will go to CERN mid-May through June 14.
Equipment:
Bring 4 TMB 2004A, 2 RAT2004A, rear card cage, and special backplane with rear connectors.
May unstructured beam period:
Use the new CCB.
ALCT signals fed through RAT module.
Use the PCcontroller-- new software (as much as possible).
Time in the peripheral crate.
Hopefully get the entire chain working to SP output.
June 7-14 structured beam period:
Add RPC inputs to RAT module, take data.
Study ME1/1 variant.
Endcap Muon
04/16/2004

11. Beyond the Test Beam/Conclusions
TMB boards:
Would like to understand the source of regulator instability.
Otherwise, the base board is ready to go into production.
Mezzanine boards:
XC2V4000’s can be procured right away.
Slight tweaks are needed to mezzanine card layout (~1 month).
RAT modules:
Boards pass bench tests.
Would like to see them working with RPC & Link Board inputs at the test beam.
Would like to see them working with the new peripheral crate backplane (June?)
Want to understand cable installation and strain relief with full crate mock-up (where, when?)
Endcap Muon
04/16/2004

12. CSC Peripheral Crate Timing
This note at
TTC distribution to peripheral crate cards
TMB-CFEB diagram
TMB-ALCT diagram
Details of L1A-LCT coincidences in TMB & DMB
TMB clocking to MPC
(CCB-TTC clocking details)
Endcap Muon
04/16/2004

13. TMB-ALCT Block Diagram
AFEB data
~2.2ns/bin
ALCT data
ALCT
latch raw data
Master clock
Synch. test pulse from
TTC command or
VME write to CCB
Main
FPGA OR
TMB Master clock
Crate Master clock
CCB
test pulse
commands
2ns/bin
Test pulse to AFEB amplifier or test strips
(select via VME write to TMB to ALCT
Slow Control FPGA register)
TMB
Latch
input ALCT
data
Main FPGA
Asynch. test pulse from
pass-
through
Adjust ALCTtx for optimal latching of ALCT output data at TMB
ALCT section
Adjust ALCTrx for optimal latching TMB output data at ALCT
output ALCT
ALCT commands
AFEB
Adjust Delay ASICs for max. probability for ALCTs to come in one BX
Internal test pulse
via VME command
to TMB
CSC Test
Pulse Strips
-RX
clock
-TX
Delay
ASICs
2ns/bin
Endcap Muon
04/16/2004

14. Endcap Muon meeting@OSU
TMB-DMB Block Diagram
DMB
CFEB
CLCT
Final
logic
TMB Master Clock, L1A
TTC/CCB Crate
Master Clock, L1A
TMB
Master Clock,
L1A
Store SCA data
command
AFF (Active
FEB Flags)
CFEBs
“hit”
AFF-L1A Coinc.
Starts CFEB digi.
& readout
CLCT FIFO
pre-trigger logic
ALCT/
CLCT/
RPC
Coincidence
Comparators
Output
FPGA
LCT-L1A
Coinc. starts
TMB readout
Readout
queue
DMB-DDU
readout
Controller
CFEB FIFOs (5)
ALCT FIFO
From ALCT
SCAs, ADCs,
Memories
From
ALCT
RPC/
RAT
L1A*CLCT
DAV Coinc.
L1A*ALCT
LCTs to
MPC
1 ns/bin
ALCT-DAV
CLCT-DAV
-DAV
Clock
DAV
Coinc.
Auto set
fixed
LCT
-read
delay
phase
Cable
Equal.
AFF
(external L1A = LHC & Test Beam operation modes)
Endcap Muon
04/16/2004

15. Endcap Muon meeting@OSU
TMB 2003A Detail
Endcap Muon
04/16/2004

16. ALCT SCSI input connectors Endcap Muon meeting@OSU
RAT2003A Detail
To TMB and 3.3v, 1.8v power
These Connectors for GND Only
Spartan 2E FPGA for RPC
RPC connectors
ALCT SCSI input connectors
Endcap Muon
04/16/2004