CLK-IN<1-0> 2x LEMOs 00

Slides:

Advertisements

Similar presentations

New Corporate Identity Poster Design Cavendish Laboratory, Department of Physics, University of Cambridge Maurice Goodrick, Richard Shaw, Dave Robinson.

Advertisements

The DAVE Card Status SCT has developed a new ATLAS trigger card “The card that no-one knew they needed, but now do” Introduction Concept & Motivation Functionality.

New Corporate Identity Poster Design Department of Physics and Astronomy, University College London Erdem Motuk, Martin Postranecky, Matthew Warren, Matthew.

SCT has developed a new ATLAS trigger card Introduction Concept & Motivation Functionality Overview Production Status ATLAS orders 03/05/20111Dave Robinson.

Georgia Tech Digital Back-end µHRG interface Curtis Mayberry School of Electrical and Computer Engineering Georgia Institute of Technology January 13 th,

Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.

ECE FPGA Design: Breakout Semester Project Proposal Derek Rose Richard Wunderlich.

Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.

DE1 FPGA board and Quartus

Silicon Programming--Altera Tools1 “Silicon Programming“ programmable logic Altera devices and the Altera tools major tasks in the silicon programming.

FPGAs and VHDL Lecture L13.1 Sections 13.1 – 13.3.

Xilinx CPLDs and FPGAs Lecture L1.1. CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA.

FPGA-Based Systems Design Flow in Action By: Ramtin Raji Kermani.

Dr. Sanatan Chattopadhyay Dr. Sudipta Bandopahyaya

Clock Distribution for IceCube June 8, 2004 Lawerence Berkeley National Laboratory Gerald Przybylski GTPrzybylski LBNL 10/13/2003.

AT94 Training 2001Slide 1 AT17 Series EEPROM Configuration Memories Atmel Corporation 2325 Orchard Parkway San Jose, CA Hotline (408)

© Copyright Xilinx 2004 All Rights Reserved 9 November, 2004 XUP Virtex-II Pro Development System.

COE4OI5 Engineering Design Chapter 2: UP2/UP3 board.

Trigger Supervisor (TS) J. William Gu Data Acquisition Group 1.TS position in the system 2.First prototype TS 3.TS functions 4.TS test status.

Nectar F2F, Barcelona /23/2015K.-H. Sulanke, DESY1 The Digital Trigger Backplane Rev. 2 power ethernet Frontend board connector L0 in /out and...

28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: COSTS ESTIMATE1 ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004 Physics & Astronomy HEP Electronics.

Section II Basic PLD Architecture. Section II Agenda  Basic PLD Architecture —XC9500 and XC4000 Hardware Architectures —Foundation and Alliance Series.

AT94 Training 2001Slide 1 AT94K Configuration Modes Atmel Corporation 2325 Orchard Parkway San Jose, CA Hotline (408) OR.

Digilab2 DIO1 Board. Digilab2 – DIO1 Boards 50 MHz clock mclk Prom socket Spartan IIE.

ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Firmware - Matt Warren1 Physics & Astronomy HEP Electronics Matthew Warren John Lane, Martin Postranecky TIM Firmware.

CALICE C&C PROPOSAL - DRAFT -4- FOR COMMENTS & CORRECTIONS A) CLOCK : a) 3x EXTERNAL INPUTS : 1) 1x Diff. LVDS ( 2x SMA ) 2) 1x LVTTL/CMOS (?) ( 1x Lemo.

South Bridge North Bridge I2CI2C SPI GPIO I2CI2C SPI GPIO FTSH Micro-B SMA JTAG USB Clock RJ45 GPIO RGMII AFE Analog UART.

South Bridge North Bridge I2CI2C SPI GPIO I2CI2C SPI GPIO FTSH Micro-B SMA JTAG USB Clock RJ45 GPIO RGMII AFE Analog UART.

Working with Xilinx Spartan 3 Embedded Systems Lab 2009.

Trigger Interface and Distribution J. William Gu Jefferson Lab 1. What is TID 2. TID Structure and functions 3. Possible usage in the system 4. TID related.

Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.

Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.

4x4 4 8x LVDS on HDMI ( 8x LVDS on SMA ? ) 8x LVDS on HDMI LVDS on SMA LVTTL on Lemo NIM on Lemo LVDS on SMA 4x LVDS on SMA 4x NIM on Lemo 2x NIM on Lemo.

VC707 Evaluation Kit Xilinx Virtex-7 In_0 GTX MHz IDELAY 8B/10B Serilizer 7 0 7IDELAY 0=>K28.5 0=>K28.1 D(15:0) K(1:0) 8B/10B IDELAYCTRL LHC_Clk.

Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France Olivier Duarte December th 2009 LHCb upgrade meeting Tests Front-end Status  Necessity.

FPGA Ethernetlink to DAQ level translation SMA/ LEMO RJ45 TLU Virtex 6 6 HDMI fanout HDMI OUT e.g. DCC-fanout HDMI IN Xilinx ML605-Board global clock trigger.

NAM S.B MDLAB. Electronic Engineering, Kangwon National University 1.

I 2 C FOR SENSORS IN THE DOM Nestor Institute Koutsoumpos Vasileios - Nestor Institute 1.

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 CMS Tracker FED CMS Tracker Two Weekly.

Cmod A7 Breadboardable Artix-7 FPGA Module

The Data Handling Hybrid

IAPP - FTK workshop – Pisa march, 2013

Lab 1: Using NIOS II processor for code execution on FPGA

Vinculum II Development Modules

AMC13 T1 Rev 2 Preliminary Design Review E. Hazen Boston University

FPGA Configuration Chris Stinson, 1998.

E. Hazen - Back-End Report

Topics SRAM-based FPGA fabrics: Xilinx. Altera..

Production TI board picture

AMC13 Status Report AMC13 Update.

Iwaki System Readout Board User’s Guide

Programming Microcontroller ADC – Analog Digital Converter

Task T - CMS at LHC Global Calorimeter Trigger

Clock & Control Card Status 29 July Martin Postranecky/Matt Warren

DAC38J84 EVM Quick Start Guide

Ext. +5V / 3A Power Conn. VME J1 VME J2 40-pin DIL HEADER USB MCU JTAG

Debug & Download DIL for USB MCU

John Lane Martin Postranecky, Matthew Warren

Digital Atlas Vme Electronics - DAVE - Module

Clock & Control Card Status 29 July Martin Postranecky/Matt Warren

40-pin DIL BREAK-OUT HEADER (incl. 4x diff. pairs 2V5 LVDS ) 3 32

DAC38J84 EVM Quick Start Guide

clock DELAY CPLD RS232 DEBUG 4x 8way DIL CLOCK ~50 MHz ASYNC SW

CLK-IN<1-0> 2x LEMOs 00

Ext. +5V / 3A Power Conn. VME J1 VME J2 40-pin DIL HEADER USB MCU JTAG

16 ( incl. 2x diff. pairs 2V5 LVDS )

DAC38J82 EVM Quick Start Guide

DAC37J82EVM, TSW14J10EVM, KC705.

The Trigger Control System of the CMS Level-1 Trigger

Implementing Logic Gates and Circuits

Presentation transcript:

CLK-IN<1-0> 2x LEMOs 00 Global Reset Switch 4-pin USB AUX. DIL 16x I/Os FPGA JTAG Prog. MODE Hex Switch. 3x STATUS LEDs ( Programmable ) 3x4 LEDs ( Program. ) Program. Reset CLK-OUT<1-0> 2x LEMOs 00 DATA-IN<7-0> 8x LEMOs 00 DATA-OUT<7-0> 8x LEMOs 00 Ext. +5V / 3A Power Conn. USB MCU JTAG 40-pin DIL HEADER VME J1 VME J2

Red LED –FPGA Prog. Xilinx PROM Prog. FPGA Switch GSI 18x4Mb SRAM Ext. 5V/3A Conn. Spartan3E FPGA Clock MUX/PLL VME Base Address A<31-28> A<27-24> 7x Supply Monitor Red LED 3x Supply OK 80.15733MHz XTAL Osc. VME J2 Clk+4 Delay Lines VME J1 Blue LED 4x Supply OK Set Serial No. SER<7-4> SER<3-0> SIL JTAG for FPGA USB Reset Switch IN<7-0> TTL/NIM Sel. Set Mod. Record MR<7-4> MR<3-0> CLK-IN<1-0> ECL/NIM Sel. CLK-OUT<1-0> ECL/NIM Sel. OUT<7-0> TTL/NIM Sel. DIL JTAG for USB MCU 40-pin DIL HEADER