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clock DELAY CPLD RS232 DEBUG 4x 8way DIL CLOCK ~50 MHz ASYNC SW

Published byIwan Kusumo Modified over 5 years ago

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Presentation on theme: "clock DELAY CPLD RS232 DEBUG 4x 8way DIL CLOCK ~50 MHz ASYNC SW"— Presentation transcript:

1 clock DELAY CPLD RS232 DEBUG 4x 8way DIL CLOCK ~50 MHz ASYNC SW
AUTO/ XTAL SW LVDS on SMA LVTTL on Lemo 8x LVDS on HDMI NIM/TTL on Lemo MPX +PLL 8x LVDS on SMA 2x LVTTL on Lemo ~50 MHz 2x NIM on Lemo X-TAL ASYNC clock LVDS on SMA SW 8x LVDS on HDMI ECL on 2pin Lemo DELAY Controls (SYNCCMD, BUSY-IN etc) 4x LVDS on SMA 4x NIM on Lemo 4x 4 SW-2 5->1 4 8x LVDS on HDMI GEN (was BUSY) LVDS on SMA CPLD (Xilinx Coolrunner XCR3128XL-7) SW-3 2->1 NIM on Lemo 8x LVDS on HDMI o/c TTL on Lemo 4 SPARE (DATA_D2L) 8x LVDS on HDMI LVTTL on Lemo RS232 PCB Header DEBUG 4x 8way DIL

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