University of California Los Angeles ALCT Technical Status Martin von der Mey University of California Los Angeles Effects of SEUs ALCT2001 status New results from radiation and cosmic ray tests SEU handling TMB-ALCT combined testing Conclusion

ALCT Status ALCT is the CSC anode trigger and readout board (anode local charged track). ALCT2000 prototype worked but… FPGAs suffered frequent “upsets” (program changes) with neutron radiation. Reload of FPGAs took “long” 150ms. Changed from Altera FPGAs to Xilinx for ALCT2001. With Xilinx reload of FPGA takes 40 ms. On-chamber electronics needs to be delivered well before installation.

ALCT Status Therefore, ALCT schedule is now a critical path item for Emu. 6 prototype alct2001’s have been tested (details follow). 6 mezzanine boards with XCV600 and 6 with XCV1000 have been produced. Pre-production batch of 30 boards has been delivered and is being assembled.

Power, computer connectors ALCT2001 Boards Power, computer connectors 80 MHz SCSI outputs (to Trigger Motherboard) Xilinx mezzanine card Main board for 384-ch type Delay/ buffer ASICs, 2:1 bus multiplexors (other side) Input signal connectors Analog section: test pulse generator, AFEB power, ADCs, DACs (other side)

ALCT Functions Inputs discriminated signals from AFEB front-end boards, provides AFEB support: Distributes power, shut-down, test pulse signals. Sets and reads back discriminator thresholds. Monitors board currents, voltages, and temperature. Delay/translator ASIC on input does time alignment with bunch crossings. Searches for muon patterns in anode signals. If found, sends information to trigger motherboard. Records input and output signals at 40 MHz in case of level 1 trigger.

ALCT2001 Modifications Radiation-related. Hardware change from Altera to Xilinx FPGAs – loads faster. Needed firmware change from AHDL to Verilog. Hard reset signal from TMB starts reload of FPGAs from rad-hard EEPROMs.

ALCT2001 Modifications Design improvements. Replace multiple ball-grid arrays (BGA) by single chip on mezzanine card. XCV600E and 1000E (identical packages) for 288/384 and 672 ch boards, resp. 40-to-80 MHz multiplexors required for single-chip design. Delay chips now allow pattern loading in order to test data path: delay chips→multiplexors → mezzanine card connectors → Xilinx ball grid inputs. 4 JTAG chains. Chains are independent. Robustness. Very stiff mezzanine card holding ball-grid array. Aluminum stiffener plate eliminates flexing.

ALCT Testing Standalone bench tests Radiation tests Cosmic ray tests ALCT-TMB test

Bench Test Results Thresholds: (ADC-DAC) +2*channel vs. DAC setting. Essentially perfect behavior. Virtex loading time (38ms). Virtex power about 1 watt.

Delay ASICs

Delay ASICs

Delay ASICs

Pulse Tests

Effect of an ALCT SEU Is a random effect. Uncorrelated between muon stations. Doesn’t affect CLCT or cathode data. A chamber is not “dead.” An inefficiency for the trigger. Is mainly an issue for ME1/1 trigger efficiency. Other stations: rates down by 4 or much more. Puts ALCT2001 into an unknown state. Makes reload of project into FPGA necessary. All on-chamber electronics should survive the worst-case radiation environment (ME1/1). Neutron Fluence (>100 keV): 6.2 x 1011 cm-2 . Total ionizing dose: 1.8 kRad.

Radiation Testing Tests done at UC Davis… Cyclotron with proton beam (63.3 MeV)

Altera (ALCT2000) SEU Measurements Calculations: SEU s = (2.3+-0.5)*10-9 cm2 per chip L = 4*104/cm2/s flux estimate ME1/1 x3 SEU s*L = 9.2*10-5/s rate per chip x3 SEU s*L = 3.7*10-4/s rate per board (4 chips) x3 Note - SEUs are better than deadtime: SEUs are uncorrelated between muon stations Muons still leave cathode LCTs for both trigger & DAQ Dead time is incurred for all of CMS if synch’ed Any bit error

Improvements Combined function of 5 chips into 1. Virtex FPGA is radiation safer than Altera. Virtex FPGA downloads logic faster from EPROM.

Altera (ALCT2000) Refresh Calculations Non-redundant logic: s *L= 9*10-5/s rate per board (4 chips) x3 Refresh every 80 sec 0.15s/80s = 0.19% refresh dead time 0.5% SEU-affected boards in ME1/1 <0.125% SEU in other stations

Altera (ALCT2000) Refresh Calculations Triple-redundant logic: s*l= 1.2*10-5/s rate per board (4 chips) x3 Refresh every 200 sec 0.15s/200s = 0.07% refresh dead time 0.24% SEU-affected boards in ME1/1 <0.06% SEU in other stations Without x3 rate safety factor, it’s about 600s between refresh, and 0.02% dead time

Virtex FPGA Loop over 64 WG, inject patterns into delay chips and read out FIFO of Virtex FPGA (Alex). Irradiate Virtex FPGA with. 50 pa beam current. 100 pa beam current. 10 pa beam current. Radiation results shows small improvements to before… SEU at 60.6 Rad compared to 59.2 Rad before… The main improvement comes due to combination of 5 chips (1 concentrator and 4 LCT chips into 1). Trigger firmware not implemented. Inject Pattern

Virtex FPGA Calculations : SEU s = 2.1*10-9 cm2 L = 4*104/cm2/s flux estimate ME1/1 x3 SEU s*l = 8.4*10-5/s rate per board Refresh every 240 s (4 min.) 0.04s/240s = 0.016 % dead time 2.02% SEU-affected boards in ME1/1 x3 <0.51 % in other stations

ALCT2000/2001 ALCT2000 SEU s = (2.3+-0.5)*10-9 cm2 per chip x4 Reload time Altera/Virtex = 0.15s/0.04s Dead time : Virtex/Altera = (1/16.4) lower !

New Radiation Test WG not found Wrong Quality

New Radiation Test Error in Rawhits Wrong DAQ

Errors Number of errors Time to error [sec] Error/time LHC [1/min] Rad dose [Rad] 1.2 +/- 0.1 Rad/sec Xsection [cm2] WG not found 116 4846 0.0065 +/- 0.0006 50.1 +/- 3.9 (2.7 +/- 0.3)*10-9 Wrong Quality 95 2785 0.0092 +/- 0.0010 35.2 +/- 3.0 (3.8 +/- 0.4)*10-9 Wrong DAQ 114 6314 0.0049 +/- 0.0006 66.5 +/- 5.2 (2.0 +/- 0.2)*10-9 Error in Rawhits 125 4623 0.0073 +/- 0.0007 44.4 +/- 3.3 (3.1 +/- 0.3)*10-9 Fatal errors 6674 0.000 +/- 0.000 00.0 +/- 0.0 0.0 +/- 0.0

Virtex FPGA Check configuration of FPGA using Xilinx verify function. Expose Virtex FPGA to 10 pa protons: 5 sec (0.001 kRad) : no errors. 10 sec (0.002 kRad) : 5 errors. 20 sec (0.005 kRad) : 3 error. 120 sec (0.031 kRad) : too many errors for reading back. SEU s = 1.73 x 10–7 cm2 . (much higher). Result : Many configuration errors. But they do not influence final results.

Virtex EPROM Move board to irradiate EPROM After radiation verify logic in EPROM using Xilinx foundation Radiated EPROM for 5 minutes at 100 pa (0.70 kRad) 500 pa (3.48 kRad) 1000 pa (7.04 kRad) Checked logic using Xilinx foundation Result : No errors were found No problem for LHC

Bus multiplexor Irradiated bus multiplexors with 1na for 5 minutes. 14.47 kRad beam current (14.47 kRad). 7.05 kRad beam current (7.05 kRad). Used Alex program to write and read patterns into. Delay lines and read back FIFO in Virtex FPGA. Results : No errors found.

Delay ASICs Move to delay ASICs. Irradiate 4 ASICs with 1 nA beam. While irradiation write and read delay lines and read back FIFO. After 20.3 kRad no error found. Results : As expected no problems with the delay ASICs. Are expected for CMS.

Slow Control FPGA Irradiate slow control FPGA with… 50 pa proton beam current 100 pa beam current 500 pa beam current Flat distribution with mean at 293.3 Rad

Slow Control FPGA No problem to expect for Spartan XL FPGA Calculations : SEU s = 0.5*10-9 cm2 L = 4*104/cm2/s flux estimate ME1/1 x3 SEU s*l = 2.0*10-5/s rate per board If refresh every 240 s (4 min.) 0.04s/240s = 0.016 % dead time 0.48% SEU-affected boards in ME1/1

ADC/DAC Test Irradiate ADCs and DACs with. 100 pa and total of 0.584 kRad (DACs). 500 pa and total of 8.172 kRad (DACs). 500 pa and total of 0.941 kRad (ADCs). No errors but damaged ADCs/DACs. No problems to expect for CMS.

Cosmic Ray Tests Carried out at U. Florida. Mounted the new ALCT2001 on-chamber. Read out anode wires. Self-triggering mode of ALCT2001 (level1). JTAG readout from ALCT2001 to Linux PC. Check trigger decision like efficiency and trigger bits (quality,wire group,…). Check noise vs. Signal ratio using radioactive source.

Rate vs. HV

Rate vs. Wire Group Long wires HV isolation buttons

Effect of “Neutron” Hits

Double LCT Rate

ALCT-TMB Testing First TMB prototype recently produced (2 available) VME readout now working ALCT-TMB interface including 80 MHz data transfer from/to ALCT has been verified

ALCT-TMB Testing Using DYNATEM to communicate from a Linux PC to the VME crate. New software has been written to control TMB functions using socket connections. Combined test of ALCT and TMB. Injected patterns into the delay lines of the ALCT using self triggering. Looked at the results on TMB side. Next step is to write the firmware to decode the multiplexed data coming from the TMB and check each bit.

Trigger Motherboard Hardware VME 9U card with interfaces to ALCT (input) 5xCFEB (input) DMB (DAQ output) CCB (clocking) MPC (trigger output) RPC link boards (optional, input) 18 boards have been produced. 2 boards have been delivered. Boards are “alive”. VME interface is debugged. ALCT clocking and I/O has been verified. 16 will be assembled following approval. Virtex-2 mezzanine card will be designed. CFEBs ALCT (Future: via transition module) RPC via transition card

Conclusions ALCT2001 prototypes works well. Xilinx loads faster: 40ms vs. 150ms. Now Virtex chip includes functions of 5 previous ones (Altera). Radiation test shows that the most of the electronic components of the ALCT2001 are radiation safe. A refresh about every 4min will minimize SEU. ALCT2001 is in good shape and ready for production. (Pre-production ongoing). Cosmic ray testing gives confidence in good working of ALCT2001. Combined test of TMB and ALCT2001 is ongoing. Good results until now.