1. FF-LYNX: 2010 & H1 2011
Luca Fanucci
Pisa, 14 Giugno 2011

2. FF-LYNX project Collaboration Goals INFN-Pisa
University of Pisa (Dept. of Information Technology)
UCSB (Physics Department)
Goals
Definition of a “standard” and flexible protocol for the integrated distribution of Timing, Trigger and Control (TTC) signals and data acquisition
Development of transmitter and receiver interfaces to serial electrical links available as IP-cores to designers of integrated circuits for future experiments

3. FF-LYNX key features Integration of control and readout
Same protocol and interfaces to distribute trigger and controls and to acquire data
Flexibility
-) Different speed options
-) Different latency options:
high priority/fixed latency (“trigger” data)
low priority/unbounded latency (“raw” data)
Protocol/Interfaces implemented in rad-tolerant IP cores

4. Outline Main results in 2010 and H1 2011
FPGA based emulator upgrade
Version V.2 of the FF-LYNX protocol (Fixed Latency Frames) fully validated in the High-Level System-C simulator and in the FPGA based emulator
FF-TC1 test circuit (Version V.1) designed and submitted for fabrication (prototypes delivered in May 2011)
Test-bed for the FF-TC1 prototypes based on “off-the-shelf” PCI-Express FPGA board (PLDA XpressGenII) and custom PCB (FF-TB)
Version V.3 of the FF-LYNX protocol (compatibility with “single-wire” links - DC-balanced encoding of frame data): on-going
Spin-Off activity: FF-LYNX & CMS EMU upgrade
Plans for H2 2011
Test and characterization of the FF-TC1 prototypes
Design of the FF-TC2 test circuit (to be submitted for fabrication in November 2011)

5. FPGA Emulator
2009:
Altera Stratix III (USB + NiOS)
2010:
PLDA Xpress-GENII (PCI-Express 8x)
The large bandwidth provided by PCI-Express 8x bus is required to perform extensive emulations with trigger data (~ 1 Gbps) while maintaining an acceptable efficiency in terms of emulation time. E.g. : trigger data rate from a CMS Tracker FE chip = 1.8 Gbps (from physics simulations); 3-4 FF-TX/RX 640 Mbps;
USB data rate (effective, half duplex) ~ 400 Mbps
 for 1 s of emulation, ~ 9 s to transfer test vectors and results
PCI-Express 2.0 8x data rate (effective, full duplex) ~ 3.6 GB/s
 for 1 sec of emulation, ~ 62.5 ms to transfer test vectors and results

6. FF-LYNX protocol evolution
Version V.1 (2009)
Two channels multiplexed in the time domain: THS channel for triggers, frame headers and synchronization patterns, FRM channel for data frames
Different speed options (4xF, 8xF, 16xF, F = reference clock  160/320/640 Mbps in LHC)
Easy coupling of interfaces to host devices: FIFO buffers and parallel ports with flow control based on data-valid/get-data lines
Robustness of critical information against transmission errors: 6-bit robust encoding for triggers, frame headers and synchronization patterns, Hamming encoding for frame descriptors
Version V.2 (2010)
Different latency options in frame transmission
Variable Latency (VL) Frames  no fixed size, no privileges in frame transmission  “raw” data
Fixed Latency (FL) Frames  fixed size, transmitted with the highest priority in TX interfaces  “trigger” data
Version V.3 (2011)
Compatibility with “single-wire” links: clock and data encoded onto one serial line
Compatibility with optical links: DC-balanced data encoding

7. FF-TC1 (1)
Rad-tolerant (TMR) TX and RX interfaces (4x, 8x and 16x) with FIFO buffers protected against SEU effects (EDAC and Scrubbing)
I2C interface and Pseudo Random Generator (PRG) for control and “built-in” test
Error counters to monitor Single and Double Event Upsets
I/O LVDS pads for clock and serial data

8. FF-TC1 (2) Size: 2mm x 2mm • Core Area: 2.135 mm2 • Package: LPCC-68
Technology: IBM CMOS 130nm (CERN/MOSIS)
Size: 2mm x 2mm
• Core Area: mm2
• Package: LPCC-68

9. FF-TC1 test bed PLDA XpressGenII board
Custom test board (FF-TB) with sockets and footprints for the FF-TC1 and FF-EMU ASICs
Xpress-GXII
FF-TB
Differential lines
Single-Ended lines
FF-TC1
Altera Stratix II

10. FF-LYNX & CMS-EMU Upgrade (1)
Replacement of Copper cables with optical links (control and readout of the Front-End electronics) in the CMS End-Cap Muon detector (ME1/1 station) foreseen during the first scheduled LHC shutdown (2013)
Limited reliability of electrical readout links (~15m - 280Mbps)
Limited space to access the new Front-End boards whose insertion is foreseen (from 5 to 7 boards in each detector chamber)
Xilinx
(Virtex)
FF-EMU FE
ASICs
DMB
O-DMB
CFEB
DCFEB
Front-End
Back-End

11. FF-LYNX & CMS-EMU Upgrade (2)
FF-LYNX protocol (V.2) for the integrated distribution of trigger and control signals: fixed latency for time-critical information (trigger and calibration pulses), unbounded latency for other control and monitoring signals
A prototype of an FF-LYNX based radiation-tolerant Front-End controller (FF- EMU) has been designed in the IBM CMOS 130nm technology and submitted for fabrication (MOSIS/CERN) in February 2011(funded by US-CMS)

12. FF-LYNX & CMS-EMU Upgrade (3)
FF-LYNX interfaces (8xF Mbps) customized with the introduction of a DC balanced encoding in data frames to make them compatible with optical links
Command encoder and decoder modules developed: transitions of trigger, control and monitoring signals are encoded as FF-LYNX frames
FF-EMU
EMU Connector Card (EMU-CC): interface between new Front-End (DCFEB) and Back-End (O-DMB) boards and existing hardware (CFEB and DMB)

13. Future Plans (H2 2011)
Test and characterization of the FF-TC1 and FF-EMU ASICs in June and July (UCSB and CERN).
Irradiation tests with X-Rays at CERN (end of July) and Protons at PSI (date to be confirmed)
Design of the FF-TC2 test circuit

14. FF-TC2 features FF-LYNX protocol V.3 in TX interfaces
Clock and data encoded onto one serial line
DC balanced encoding of frame data
Standard clock data recovery in FPGA devices
Improved SER/DES devices
Manual placement & routing of standard cells
Custom cells (if required)
Improved radiation tolerant FIFOs
Interleaving in FIFO arrays
More efficient encoding (lower area and power consumption)
High speed rad-tolerant differential pads
Self-biased amplifiers with automatic compensation of total dose effects

15. UCSB Support
Support for two young engineers (MS thesis on the FF-LYNX project) and one PhD student of the University of Pisa (DII-EIT) :
G. Bianchi (February 2010 / October 2010): System level modeling of FF-LYNX based links - Integrated Simulation Environment
C. Tongiani (February 2010 / October 2010): FPGA based emulators of FF-LYNX based links
N. Costantino (April 2010 / October 2011): Design in standard CMOS sub-micron technologies of integrated circuits implementing FF-LYNX interfaces as radiation tolerant and low power IP cores

16. Thanks for your attention !!