1. Irradiation Test of the Spartan-6 Muon Port Card Mezzanine
Devices Under Test
XCF32P PROM
XC6SLX150T FPGA

2. Firmware for the FPGA Test
■ Two pipeline chains, 16-bit wide and 20,000 steps deep
■ Pseudo-Random Bit Stream Generators as data sources
■ Only the Configurable Logic Blocks (CLB) and Flip-flops (FF) are used (close to
realistic MPC firmware), running at 40MHz
■ ~22% of the FPGA resources used (~19% for the present MPC design)
■ Common reset
■ Error signal is counted externally by the Agilent 53132A counter
■ LVDS link (~8 m long) between the MPC residing in the irradiation area and the
counter in the control room
● 4 JTAG lines
● Error signal
● Hard reset to reload the FPGA from EPROM 2

3. MPC Under Beam at UC Davis
■ 66 MeV proton accelerator at Crocker Nuclear Laboratory, UC Davis
■ Wide range of beam fluxes typically from 104 to 109 p/cm2 /s 3

4. Xilinx XC6SLX150T-3FFG900C FPGA Tests
■ Irradiated with 1 kRad at a rate of ~1 Rad/sec (convenient to detect SEU)
● 75 Single Event Upsets (SEU):
- Counter counts +1 (most errors) [Bit flip in the pipeline chain; self-recoverable]
- Counter counts continuously
- Counter jumps to some large number, then counts +1
- Counter freezes at some point
[Pipeline chain or reset circuitry is broken; need to reload the FPGA from EPROM]
● 5 to 15 seconds between SEU
● Average dose to get an error ~13 Rad. With the accumulated fluence of 3*1011 protons/cm2,
the cross section of SEU is 75 / 3x1011 = 2.5x10-9 cm2 .
● Assuming 10-year fluence of ~1011 neutrons per cm2 [1] at full LHC design luminosity,
the worst case SEU rate would be 2.5x10-9 cm2 x 1011 neutrons/cm2 / 5x107 sec = 5x10-6, or
1 SEU in ~ 55 hours per device [1]
■ Irradiated with 30 kRad at a rate 80 Rad/sec (10 years of LHC exposure in the ME1/1 area with a
safety factor 3)
● Many upsets
● FPGA survived the test
■ Irradiated with 100 kRad at a rate of 360 Rad/sec
■ Irradiated with ~300 Rad at a rate of ~1 Rad/sec again (repeat of first test)
● 50 SEU in 5 minutes
● Average dose to get an error ~6 Rad, ~2 times higher than in test 1
● FPGA is fully functional 4

5. Xilinx XCF32P EPROM Test
■ Irradiated with 1 MeV equivalent fluence at ~10.5 *1012 n/cm2
at the TAMU cyclotron in April 2013
■ Equivalent to ~30kRad, or 30 years of LHC exposure in ME1/1 area
■ Device was read back; not a single bit change, as expected 5