1. Effect of an ALCT SEU Much-overlooked good stuff
Is a random effect
Uncorrelated between muon stations
Doesn’t affect CLCT or cathode data
A chamber is not “dead”
An inefficiency for the trigger
Is mainly an issue for ME1/1 trigger efficiency
Other stations: rates down by 4 or much more
Much-overlooked bad stuff
Puts ALCT into an unknown state

2. SEU Measurements Calculations: Refresh every 40 sec:
SEU s = ( )*10-9 cm2 per chip
L = 4*104/cm2/s flux estimate ME1/1 x3
SEU s*L = 9.2*10-5/s rate per chip x3
SEU s*L = 3.7*10-4/s rate per board (4 chips) x3
Refresh every 40 sec:
0.15s/40s = 0.37% refresh deadtime
0.7% SEU-affected boards in ME1/1
<0.18% SEU in other stations
Note - SEUs are better than deadtime:
SEUs are uncorrelated between muon stations
Muons still leave cathode LCTs for both trigger & DAQ
Deadtime is incurred for all of CMS if synch’ed
Any bit errors during self-test

3. New SEU Measurements
LCT chip measurements hot off the press (10/5/2000):
Separate out Trigger errors from DAQ hit readout errors
have/don’t have trigger, or
wire group wrong, or
pattern or accelerator bits wrong
Non-redundant logic trigger errors:
25% of previous measurement
Triple-redundant logic trigger errors:
3.3% of previous measurement

4. New Refresh Calc’s Non-redundant logic: Triple-redundant logic:
s *L= 9*10-5/s rate per board (4 chips) x3
refresh every 80 sec
0.15s/80s = 0.19% refresh deadtime
0.5% SEU-affected boards in ME1/1
<0.125% SEU in other stations
Triple-redundant logic:
s *L= 1.2*10-5/s rate per board (4 chips) x3
refresh every 200 sec
0.15s/200s = 0.07% refresh deadtime
0.24% SEU-affected boards in ME1/1
<0.06% SEU in other stations
Without x3 rate safety factor, it’s about 600s between refresh, and 0.02% deadtime

5. SEU Handling Triple-redundant logic gives early warning
single upset is okay (warning)
double upset zeroes out the ALCT trigger result
active protocol added: CLCT can poll ALCT for upsets, or ALCT can volunteer upsets
Periodic self-tests cycle all of the trigger logic plus the Concentrator
10 Hz of 88 us testing allowed by pixel refresh
active protocol: CLCT initiates self-tests in smooth way
Hooks are there for several options:
centralized periodic refresh
record number, time of SEUs via data path to DAQMB
report SEU to central trigger control (but how from CLCT?)
autonomous but recorded refresh

6. University of California Los Angeles
ALCT SEU Mitigation
Martin von der Mey
University of California Los Angeles
Effects of SEUs
Old radiation test results
New preliminary results
Trigger output only rate
Triple voting logic rate
SEU handling
Altera vs. Xilinx issues

7. New results Radiation tests at UC Davis
Cyclotron with proton beam energy 63.3 MeV

8. Virtex chip Radiation results shows small improvements to before…
Mean lies at Rad compared to 59.2 Rad before…
The main improvement (factor 5) comes due to combination of 5 chips
(1 concentrator and 4 LCT chips into 1).

9. Virtex Eprom Move board to irradiate Eproms
After radiation verify logic in Eprom using
Xilinx Foundation
Result :
Radiated Eprom for 5 minutes at
100 pA (0.70 kRad)
500 pA (3.48 kRad)
1000 pA (7.04 kRad)
Check logic using Xilinx Foundation
No errors were found….No problem for LHC…

10. Bus multiplexor Irradiated bus multiplexors with 1nA for 5 minutes
14.47 kRad beam current
7.05 kRad beam current
Used Alex program. Write and Read Delay
Lines…
Results :
No errors found…

11. Delay ASICs Move to Delay ASICs Irradiate 4 ASICs with 1 nA beam.
While irradiation write and read delay
Lines…
After 20.3 kRad no error found…
As expected no problems with the Delay ASICs
are expected

12. Slow Control FPGA Irradiate Slow Control FPGA… With…
50 pA proton beam current.
100 pA beam current
500 pA beam current.
Flat distribution…Mean is
293.3 Rad…much higher
than for the Virtex FPGA
No problem to expect for
Spartan XL FPGA

13. Other Issues Triple-logic not possible in some places
for voting logic itself
Concentrator FPGA - too many miscellaneous I/O and too many possible states
Result of SEU is unpredictable (haywire?)
Minimizing rate of SEUs is good, but
Smooth detection and handling is MORE important
Altera 20K series may have different (lower?) SEU cross-section
A rough estimation might be gotten with demux test board

14. Xilinx vs. Altera: Fact and Fiction
3 claims from the ESR report:
Xilinx loads faster
Xilinx is more radiation tolerant
Xilinx may be reloadable by section
Reality:
We have seen NO evidence that Xilinx is more radiation tolerant.
ALCT logic and test procedure were both significantly different from CFEB
Very unlikely that Xilinx can be reloaded in section
Also problematic to read back and check configuration - get SEUs during read process (Durkin)
Only verified advantage of Xilinx: faster loading
5ms vs 150ms

15. More on Xilinx vs Altera
Impossible to use Xilinx flat packs (I/O count too small)
BGA assembly, testing, and reliability issues
Design consideration: can refresh from CLCT directly
eliminates EPROMs on ALCT board
will be ~120ms for Xilinx or Altera
Conversion requires language change
Mainly AHDL to VHDL, or to Verilog HDL
Expect 3-4 month conversion time
Expect ~2 months of radiation tests