Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures SAJID BALOCH Prof. Dr. T. Arslan1,2 Dr.Adrian Stoica3 Supervisory Team

ACRONYMES SEU (Single Event Effect) SET (Single Event Transient) SEB (Single Event Burnout) SEL (Single Event Latch-up) Cfg (Configuration) EDAC (Error Detection and Correction) SoC (System on Chip) FPGA (Field Programmable Gate Array) DEU (Double Event Upset) TEU (Triple Event Upset ) MEU (Multiple Event Upsets) Fills critical Gap between Discrete logic and Mask Programmable Arrays Commercial Applications, Military Applications, Avionics applications Requirements for space application: low power, less area, high reliability, FTTM SRAM Pass transistor based switches and controlled by state of SRAM bit Anti Fuse programmable switch forms a low resistance path between to metal layers EPROM switch is floating gate transistor which is turned on by injecting charge onto the floating gate (EPLDs or EEPLDS) SRAM and Antifuse are volatile ACTEL and Xilix are the key player in Aerospace FPGAs Honeywell -> Actel Aeroflex -> Quick Logic Faults due to Radiation Permanent Faults (due to SEL, SEB etc) Transient Faults (due to SEU etc) Single event upsets are produced by single charged particle that hits over integrated circuits. The SEU targets the drain of OFF transistor. When a single charged particle strikes an integrated circuit, it loses energy via the production of electron hole pairs result in a dense ionized track in the region. This transient causes a transient current pulse. This abnormal behaviour can cause faults in integrated circuits which can be of Permanent in nature or it can be a transient fault. Permanent Faults are classified as Single event latch up and single event burnouts etc. The transient faults are termed as single even Upsets

RECONFIGURABLE ARCHITECTURES a) FPGAs - SRAM - Anti Fuse - EPROM b) Reconfigurable SoC - General purpose - Domain Specific Re-Configurable SoC Architecture

RADIATION EFFECTS RE-CONFIGURABLE ARCHITECTURES PERMANANT FAULTS (due to SEL, SEB etc) TEMPORARY FAULTS (due to SEU etc) Single event upsets are produced by single charged particle that hits over integrated circuits. The SEU targets the drain of OFF transistor. When a single charged particle strikes an integrated circuit, it loses energy via the production of electron hole pairs result in a dense ionized track in the region. This transient causes a transient current pulse. This abnormal behaviour can cause faults in integrated circuits which can be of Permanent in nature or it can be a transient fault. Permanent Faults are classified as Single event latch up and single event burnouts etc. The transient faults are termed as single even Upsets

SEU MITIGATION TECHNIQUES a) HARDWARE REDUNDANCY - Dual Modular Redundancy (DMR) - Triple Modular Redundancy (TMR) - EDAC Codes - Process Technology b) TIME REDUNDANCY c) COMBINATION (Hardware & Time) so far SEU hardening can be done in three ways Hardening by Technology – where a specific technology process for fabrication is used. For example an epitaxial CMOS (Epi-bulk) device or SOI (silicon on insulator) epi-bulk is very efficient in SEL but not as good in SEU. SOI partially eliminates SEU Hardening by Design – where logic structures are modified to achieve the SEU immunity, examples are TMR (triple modular redundancy) hardened memory gate cells, hardened memory cells using feedback structures, Error correcting Codes ( Hamming Codes etc)

Radiation Hardening SEU EFFECTS TRANSIENT FAULTS (Data Memory etc) PERMANANT FAULTS (Cfg. Memory)

SEU EFECTS Synchronous Circuits

SEU EFECTS Configuration Memory

SEU EFECTS ROUTING OF A SIGNAL

Proposed SEU/SET Mitigation Technique based on: Temporal Data Sampling Weighted Voting Salient Features of The Proposed Technique: Auto Correction Mechanism for 100% SEU Recovery 100% Double Fault Recovery Voter Faults Recovery

Temporal Sampling Primary Section Secondary Section

TEMPORAL SAMPLING Clock Scheme 3 derivates of Main Clock Each Clock is Phase shifted 25% duty Cycle

Weighted Voter Circuit Minimized Term X4.X3.X0 + X5.X3.X0 + X5.X4.X0 + X4.X3.X1 + X5.X3.X1 + X5.X4.X1 + X4.X3.X2 + X5.X3.X2 + X5.X4.X2 + X5.X4.X3 + X3.X2.X1.X0 + X4.X2.X1.X0 + X5.X2.X1.X0

SEU in Secondary Section Case Example SEU in Secondary Section Node Before SEU After Voting Weights ‘1’ ‘0’ Total Votes 1 2 - 8 3 5 4 6

Case Example Multiple Bit Upset Node Before SEU After Voting Weights ‘1’ ‘0’ Total Votes ‘1’ ‘0’ 1 2 - 5 4 3 6

Hardware Implementation of Proposed Scheme with Auto-Correction Mechanism

Single Event Transition Fault Data / Clock

SEU/SET Simulator SEU’s can be injected at instance SEU of any duration can be injected Multiple upsets can be injected

Performance Analysis Fault Coverage  Mitigation Scheme %age Fault Tolerance SET SEU DEU TEU Proposed Scheme 100% 50% F. Lima etal Scheme 63% - D. Mavis etal Scheme 32% 18%

Performance Analysis Area Overhead Results are based on: 0.13µm CMOS technology