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Binocular Bilateral Controller: A Hardware Fault Tolerant Implementation Marylène Audet March 2001 VLSI Testing.

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Presentation on theme: "Binocular Bilateral Controller: A Hardware Fault Tolerant Implementation Marylène Audet March 2001 VLSI Testing."— Presentation transcript:

1 Binocular Bilateral Controller: A Hardware Fault Tolerant Implementation Marylène Audet March 2001 VLSI Testing

2 Agenda Goals The Binocular Controller Fault-Tolerant Designs Conclusion

3 Goals Implement a binocular controller using eye movements model Design a fault-tolerant system Simulate and test the controller

4 The Binocular Controller Conjugate Component (E C ) : average direction in which eyes are pointed Vergence Component (E V ) : angle subtended by two lines of sight EC = 1/2 (E R - E L ) EV = (E R +E L )

5 The Binocular Controller (2)

6 The Binocular Controller (3)

7

8 The Binocular Controller (5) Digital Implementation requires delay insertion Slow Clock (order of KHz) 12-bit digitized Inputs All parameters shall be programmable via a CPU or switches Target technology is FPGA (Xilinx) Ref: “Binocular Coordination Providing Stable Tracking and Rapid Reorientation Using A Bilateral Controller Inspired By Nature”, Ross Wagner,PHD Thesis, McGill University, 1997 FOR MORE INFO...

9 Fault-Tolerant Designs Introduction MTBF Triple Modular Redundancy Self Purging Techniques Sift-Out Modular Redundancy Rollback Implementation or Time Redundancy Berger and Weight-Based Codes

10 Fault-Tolerant Designs (2) Fault-tolerant Design are used in the Military and Aerospace, Medical, Banking, etc. industries Deep-submicron technology: compensates low yields. Goal: Very High Reliability measured using MTBF evaluations. Uses Concurrent Built-In Self-Test and Redundancy Techniques.

11 MTBF MTBF: Mean-Time Between Failures For example: –Processor of 100 Million Instruction Per Seconds (100 MIPS) –Reliabiltiy Factor R(t) = (0.9) 12 -> 1 Failure/10 12 Events –MTBF = (10 12 ) * (10 -8 ) = 10 000 Seconds ~ 2.7 Hours

12 Triple Modular Redundancy As good as its Voter Voter must be Totally Self-Checking Redundancy cannot be tested off line -> must have a way of disabling the redundant circuit High Area Cost Module Partitioning

13 Self-Purging and Sift-Out Self-Purging: Remove Faulty Path by Comparing –Problem: may require an exterrnal arbiter if there is a tie –Requires feedback from Voter Sift-Out: all decision done by controller but Voter is free from controller.

14 Rollback Implementation Basics: Checkpoints exists to fall-back Must have a state diagram detecting permanent faults Checker can be any encoder

15 Error Coding Techniques Concurrent Checking / on-line. Checker detects 1->0 and 0-> 1 Transitions Errors. Checkbits can be positional (Hamming) / non-positional (Berger) within the output vector Can assign a “weight” to each output.

16 Conclusion Design Partitioning for Modular Redundancy: Adders and Multipliers Checking Algorithm for Sift-Out Implementation Verify against analog counterpart.


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