Challenges in Nanoelectronics: Process Variability Dr. B.P. Harish, Assistant Professor, Dept. of Electrical Engineering, University Visvesvaraya College of Engg., Bangalore University, Bangalore.

Agenda Introduction Nanoelectronics - Challenges Process variability issues Summary

Introduction Technology scaling has been the driver of semiconductor industry. Scaling

Scaling benefits With technology scaling, over a 18-24 months period, – - Frequency scales up by 43% - Area scales down by 50% - Energy per transition comes down by 30- 35%. These benefits are no longer there – Moore’s law is slowing down.

Nanoelectronics - Challenges Leakage power contributes about 33% of total power and increases with scaling. - subthreshold leakage increases by about 3-5X. - gate leakage increases by 30X, across process generations. Photolithography challenges – pattern transfer issues. Reliability issues - as doping increases, electric fields in the device are increasing. Process complexity is increasing – so also costs. Process control is becoming challenging. Process variability – device and circuit performance is becoming unpredictable.

Process Variability: Introduction Tox Tsp Na Xj Oxidation Deposition Implantation Diffusion Speed Dynamic power Static power Yield Id CL Vt Vt Process variability - increasing with technology scaling. Feature sizes scaled more rapidly than process tolerances - significant device variability. Variability impacts all design goals – performance, power budget and reliability. Need to achieve robust device/circuit performance, in the presence of process variations.

Typical Variation in Parameter Large Variance Small Variance Distribution of actual performances, around nominal performance metrics, in a population of chips. Vt Vt Urgent need to tighten this distribution - at process design level - at device design level - at circuit design level

Taxonomy of Variation Sources of variation Process variations Environmental variations Inter-die variations Intra-die variations Systematic variations Random variations New design methodologies ??? (Vdd and Temperature) (Corner based analysis) Extrinsic variations Intrinsic variations

Frequency and Leakage Variations Source: Intel 30% variation in frequency and 20X variation in chip leakage. Significant yield loss – both parametric and functional yield.

Deviation in Transistor Parameters Threshold voltage Subthreshold slope Technology generation Technology generation Drive current Subthreshold leakage Technology generation Technology generation Source: Tang et al, TVLSI 1997. Process variations – barrier to technology scaling.

Variability: Leakage Power Measured variations in chip level leakage – 20X. 2 Ao variation in Tox can lead to 10X change in gate leakage. Power conscious CAD tools and methodologies can help achieve technology independent power gains of 3X to 5X. Variability-aware statistical chip level leakage power estimation techniques are necessary.

Solutions: Device Design Level Whether Gate-to-Source/Drain Overlap Length (Lov) can be an effective design parameter? If so, what is the desired overlap length that results in better variability?

Variability: Role of Lov It has been established that – - as Lov reduces, Ion reduces with reduction in Ion variability, degrading the device performance - Trade-off exists between drive current and its variability. - as Lov reduces, delay increases with decrease in delay variability - Trade-off exists between delay and its variability. Lov of 0 nm is recommended at 65 nm gate length for optimal combination in delay and delay variability. Lov of 0 nm also results in better performance in analog and digital applications.

Summary An overview of some of the challenges in nanoelectronics is presented. Process variability issue is discussed and some solutions proposed.

Thank You