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Statistical Full-Chip Leakage Analysis Considering Junction Tunneling Leakage Tao Li Zhiping Yu Institute of Microelectronics Tsinghua University.

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Presentation on theme: "Statistical Full-Chip Leakage Analysis Considering Junction Tunneling Leakage Tao Li Zhiping Yu Institute of Microelectronics Tsinghua University."— Presentation transcript:

1 Statistical Full-Chip Leakage Analysis Considering Junction Tunneling Leakage Tao Li Zhiping Yu Institute of Microelectronics Tsinghua University

2 2 Outline Motivation Motivation Junction Tunneling Leakage – Circuit Level Analysis Junction Tunneling Leakage – Circuit Level Analysis –Simple inverter –Multi-input gate Statistical Full-Chip Leakage Analysis Technique Statistical Full-Chip Leakage Analysis Technique –Modeling of process-induced parameter variations PCA & ICA PCA & ICA –Sum of leakage components Experimental Results Experimental Results Summary Summary

3 3 Leakage and Process Variations Leakage power becomes a major component of the total power. Leakage power becomes a major component of the total power. Process variation has a significant impact on leakage. Process variation has a significant impact on leakage. 50 100 150 200 250 0 0.25  0.18  0.13  0.1  Leakage Power Active Power Power (W) Feature Size Scale Down 0.18 μm0.09 μm 65 nm

4 4 Major Leakage components Subthreshold leakage Subthreshold leakage Gate oxide leakage Gate oxide leakage Junction tunneling leakage Junction tunneling leakage Gate Source n+ Bulk Drain Subthreshold Leakage I sub Gate Leakage I gate Junction tunneling leakage

5 5 Overview of Related Works Previous works on statistical full-chip leakage computation Previous works on statistical full-chip leakage computation –Computation of PDF of full-chip leakage Approximate process variations as Gaussian distributions Approximate process variations as Gaussian distributions Finding full-chip leakage by summing up independent lognormals Finding full-chip leakage by summing up independent lognormals R. Rao ISLPED03,H. Chang ICCAD 03, H. Chang DAC05, X. Li DAC06, et al. R. Rao ISLPED03,H. Chang ICCAD 03, H. Chang DAC05, X. Li DAC06, et al. Most of the previous works ignored Most of the previous works ignored –Effect of Non-Gaussian parameters –Junction tunneling leakage

6 6 Outline Motivation Motivation Junction tunneling leakage – Circuit level analysis Junction tunneling leakage – Circuit level analysis –Simple inverter –Multi input gate Statistical Full-chip leakage analysis technique Statistical Full-chip leakage analysis technique –Modeling of process-induced parameter variations PCA & ICA PCA & ICA –Sum of leakage components Experimental Results Experimental Results Summary Summary

7 7 Simple Inverter When input = 0V When input = 0V –NMOS: maximum & Can be independently calculated and added for total leakage Can be independently calculated and added for total leakage –PMOS: gate oxide leakage – small and ignored When input = When input = –NMOS: gate oxide leakage –PMOS: subthreshold leakage and junction tunneling leakage 0 0

8 8 Multi input gate: general approach If all inputs have a high state If all inputs have a high state –Analysis is similar to the that of the inverter At least one input is low At least one input is low –Combination of,,and –Approach: distinguish 6 different scenarios

9 9 Total leakage current of a chip: Total leakage current of a chip: Computation of Total Chip Leakage Input pattern independent approach Input pattern independent approach –Direct computation: 2 k input vector states for a k-input gate –Applying dominant states of Leakage of stack at state i is not always independent Leakage of stack at state i is not always independent –Interactions of I sub, I gate and I junc need to be considered –Analyzing leakage current of stack by input state : probability of input vector state i of the j th gate can be either the leakage for a fixed input vector or the average leakage current

10 10 Dominant States of Leakage Current Case (a) (c): dominate states of I gate Case (a) (c): dominate states of I gate NMOS-Transistor Stack Interaction between I sub and I gate Interaction between I sub and I gate D. Lee et. al. at DAC03 C. Oh et. al. at DAC99 D. Lee et. al. at DAC03 Dominant states of junction tunneling leakage I junc Dominant states of junction tunneling leakage I junc –States with the “on” transistors connected to the output node (stack effect ) –Only k dominant states for a k-input gate Case (a) (b): dominate states of I sub Case (a) (b): dominate states of I sub

11 11 Results: Leakage estimation for 4-NAND The error of the proposed analysis method over SPICE The error of the proposed analysis method over SPICE Average ~1.5% over all input states Average ~1.5% over all input states Maximum error = 4.5% @1110 Maximum error = 4.5% @1110

12 12 Outline Motivation Motivation Junction tunneling leakage – Circuit level analysis Junction tunneling leakage – Circuit level analysis –Simple inverter –Multi input gate Statistical Full-chip leakage analysis technique Statistical Full-chip leakage analysis technique –Modeling of process-induced parameter variations PCA & ICA PCA & ICA –Sum of leakage components Experimental Results Experimental Results Summary Summary

13 13 Proposed Analysis Method Highlights Incorporates both Gaussian and non-Gaussian parameters Non-Gaussian and Gaussian variables transformed to independent basis with PCA/ICA Uses closed form PDF/CDF expressions Moments matching-based PDF/CDF extraction Fast algorithm for the sum up of leakage components Three kinds of leakage components are considered Inputs are moments of varying process parameters Easier to obtain moments from process data files

14 14 Outline Motivation Motivation Junction tunneling leakage – Circuit level analysis Junction tunneling leakage – Circuit level analysis –Simple inverter –Multi input gate Statistical Full-chip leakage analysis technique Statistical Full-chip leakage analysis technique –Modeling of process-induced parameter variations PCA & ICA PCA & ICA –Sum of leakage components Experimental Results Experimental Results Summary Summary

15 15 Experimental Results Comparison of our results with Monte Carlo simulations Comparison of our results with Monte Carlo simulations Comparison with Gaussian modeling of parameters Comparison with Gaussian modeling of parameters BenchmarkOur Method Error ((Our-MC)/MC)%Gaussian Error ((Old-MC)/MC)% Name#Cells#Grids µ σ95% Pt5% Pt µ σ95% Pt5% Pt C7552523564-1.633.023.843.916.3223.4424.66 4.56 C5315376864-1.07-2.82-4.09-3.685.6917.5620.31 4.89 C6288255216-1.15-2.143.523.615.9814.6314.89 3.11 C35402491160.711.56 2.972.884.9610.2315.34 -3.16 C2670185416-0.811.342.902.774.788.8411.13 2.34 C1908119716-0.64-0.98-2.452.123.458.028.98 4.34 C880556 4-0.23-0.59-1.26-1.322.126.149.32 1.23 C432273 4-0.07-0.23-0.98-0.841.295.994.14-2.01

16 16 Outline Motivation Motivation Junction tunneling leakage – Circuit level analysis Junction tunneling leakage – Circuit level analysis –Simple inverter –Multi input gate Statistical Full-chip leakage analysis technique Statistical Full-chip leakage analysis technique –Modeling of process-induced parameter variations PCA & ICA PCA & ICA –Sum of leakage components Experimental Results Experimental Results Summary Summary

17 17 Summary A fast approach to compute total leakage current A fast approach to compute total leakage current –Considering,,and –Average error 1.5% Both Gaussian and Non-Gaussian parameters are considered Both Gaussian and Non-Gaussian parameters are considered –PCA and ICA are employed as preprocessing steps Sum the leakage to get a final result Sum the leakage to get a final result Algorithm has a complexity of Algorithm has a complexity of

18 18 Thanks!

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