1. Institute of Digital and Computer Systems 1 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Chapter 5 Finding Peak Performance in a Process Closing the Gap between ASIC & Custom

2. Institute of Digital and Computer Systems 2 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Overview  Process and operating conditions  Statistical process variation  Impact of process improvements on the achievable speed  Impact of different process implementations of the same technology  Difference between ASIC and custom due to process and operating conditions  Possible performance improvement in ASIC

3. Institute of Digital and Computer Systems 3 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Process and Operating Conditions  Standard cell libraries are characterized for two features  Operating conditions: nominal supply voltage and operating temperature;  Different process: slow (worst case), typical and fast ASIC synthesized for slow process condition: high yield at the post layout clock frequency ASIC designers typically assume w. c. process  Speed bin chips  Chips are tested and sold according to the supported speed  Operating conditions  Worst case: 100° or 125°, 90% of Vdd They can be quite realistic  Typical conditions: 25°, nominal Vdd  Worst case power consumption corresponds to highest operating conditions (high frequency, fast process, high operating voltage, low temperature)

4. Institute of Digital and Computer Systems 4 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Supply Voltage and Drive Strength  Larger drive current implies more speed  It can be increased by increasing the width of transistors, the supply voltage, decreasing the threshold voltage or the load capacitance  Gates with wider transistors (higher drive strength) are used to reduce the delay on critical paths  It increases the power consumption  The same happens increasing the supply voltage  It increase also the power dissipation during gate switching  Decreasing the threshold voltage, static power consumption can grow  ASIC designer can usually exploit libraries with different transistors width, decide to provide different supply voltage and choose among few libraries with different threshold

5. Institute of Digital and Computer Systems 5 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Higher Temperature vs. Circuit Speed  Higher temperature reduces speed  It increases wire resistance, transistor resistance and decreases the drive current  It increases power consumption  Leakage current grows  Operating conditions set at 125° is a conservative estimates for ASIC  Spot temperature can be higher than the average one  Operating temperature is limited by the ambient temperature and available cooling methods  Many embedded applications cannot use advanced cooling methods  Higher power chip dissipates more heat

6. Institute of Digital and Computer Systems 6 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Custom vs. ASIC Operating Conditions  Increasing the supply voltage is a common technique to over-clock custom chips  Sometimes chips in a low speed bin doesn't work using lower voltage  But this increases the power dissipation  More exotic cooling devices can be used to lower temperature and improve performance  But this generally doesn’t justify the cost of the cooling mechanism even in high-performance CPUs  They can have also high power consumption  Heat sinks and fans significantly increase the cost of a the overall system  Also packaging can affect the speed  In the 1GHz Alpha, using flip chip instead of wire bond increase by 10% the operating frequency

7. Institute of Digital and Computer Systems 7 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Performance Penalty Imposed by the Tight Power Constraints of ASIC Design  Lack of cheap packaging solutions  Celeron uses socketable micro-FCPGA or surfaced mount micro- FCPGA High level of power dissipation  Advanced ASIC technologies are TEPBGA or PBGA  If placed in a ASIC packaging the Celeron processor would be limited to 600MHz or 530MHz, instead of 1100MHz

8. Institute of Digital and Computer Systems 8 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Comparison of ASIC Process and Operating Conditions  Clock frequency for some high speed ASIC CPUs

9. Institute of Digital and Computer Systems 9 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Chip Speed Variation Due to Statistical Process Variation  Wafer processing  Several types of process variation  Line-to-line, batch-to-batch: difference in masks, steppers and optics  Wafer-to-wafer: distance between wafer and optics  Die-to-die, intra-die: varying illumination and lens aberration  For marketing purposes, AMD and Intel will bin processors to slower clock frequency than necessary  Sometimes over-clocking is a good idea  The variation decreases as the process matures

10. Institute of Digital and Computer Systems 10 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Continuous Process Improvement  Top semiconductor foundries continuously improve the process technology  Difference of performance inside the same process generation  Due also to supply voltage, chips binned to slower frequencies, process improvements, design optimization

11. Institute of Digital and Computer Systems 11 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Speed Difference Due to Alternative Process Implementations  Copper wiring vs. aluminum wiring  Aluminum has higher resistance and performance is lower  Silicon on insulator vs. bulk CMOS  20%-25% faster, less power  Process difference between custom and ASICs  Custom 20% - 40% faster than ASICs  ASIC foundries offer several process within a process generation  Slower, high-density, high-speed  Slower are cheaper

12. Institute of Digital and Computer Systems 12 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Effects of Process and Tuning  Advances in process combined with additional tuning can measurably increase the performance of a given design  Some examples

13. Institute of Digital and Computer Systems 13 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Process Technology for ASICs  After a process improvement, the library must be characterized again and redesigned  If not, 20% of improvement lost  ASIC may not have access to the best fabrication plants  Fabrication plants guarantee a fixed speed  Worst case design  Usually also faster chips are produced  ASIC may prefer slower chips for marketing purposes  For ASIC, the process migration is easier  It requires only to retarget the ASIC library  However custom design can take full advantage of the process

14. Institute of Digital and Computer Systems 14 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Potential Improvements for ASICs  ASIC designers can test chips to see if performance is better than w. c. estimate  20%-30% improvement in speed over w. c.  Speed bin  Supply voltage can be increased to speed up the chip  Higher temperature is not a good choice, because of the cost of packaging technologies

15. Institute of Digital and Computer Systems 15 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Thank you!