EE141 Chapter 3 VLSI Design The Devices March 28, 2003

Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-sub-micron effects Future trends

The Diode Mostly occurring as parasitic element in Digital ICs n p B A SiO 2 Al Cross-section of pn -junction in an IC process One-dimensional representation diode symbol Mostly occurring as parasitic element in Digital ICs

Depletion Region

Diode Current

Models for Manual Analysis

Junction Capacitance

Secondary Effects Avalanche Breakdown 0.1 ) A ( I –0.1 –25.0 –15.0 I D –0.1 –25.0 –15.0 –5.0 5.0 V (V) D Avalanche Breakdown

Diode Model

SPICE MODELS SPICE: Simulation Program with Integrated Circuit Emphasis, by UCB in early 1970’s. Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-empirical - Based on curve fitting to measured devices Level 4 (Berkeley Short-Channel IGFET Model, BSIM3v3): Empirical - Simple and Very Popular,. Full-fledged BSIM3v3 model (denoted as LEVEL 49) covers over 200 parameters.

SPICE Parameters

What is a Transistor? A Switch! |V GS | An MOS Transistor

The MOS Transistor Polysilicon Aluminum/Cu

MOS Transistors - Types and Symbols G G S S NMOS Enhancement NMOS Depletion D D G G B S S NMOS with PMOS Enhancement Bulk Contact

Threshold Voltage: Concept

The Threshold Voltage

The Body Effect

Current-Voltage Relations 0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Resistive Saturation VDS = VGS - VT Quadratic Relationship

Transistor in Linear

Transistor in Saturation Pinch-off

Current-Voltage Relations Long-Channel Device

A model for manual analysis

Current-Voltage Relations The Deep-Submicron Era -4 V DS (V) 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Early Saturation Linear Relationship

Velocity Saturation u ( m / s ) u = 10 x = 1.5 x (V/µm) 5 sat n c Constant velocity Constant mobility (slope = µ) x c = 1.5 x (V/µm)

Perspective I V Long-channel device V = V Short-channel device V V - V GS DD Short-channel device V V - V V DSAT GS T DS

ID versus VGS linear quadratic quadratic Long Channel Short Channel 0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V GS (V) I D (A) 0.5 1 1.5 2 2.5 x 10 -4 V GS (V) I D (A) linear quadratic quadratic Long Channel Short Channel

ID versus VDS Resistive Saturation VDS = VGS - VT Long Channel 0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Resistive Saturation VDS = VGS - VT -4 V DS (V) 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Long Channel Short Channel

A unified model for manual analysis G B

Simple Model versus SPICE 0.5 1 1.5 2 2.5 x 10 -4 Velocity Saturated Linear Saturated VDSAT=VGT VDS=VDSAT VDS=VGT (A) I D V (V) DS

A PMOS Transistor Assume all variables negative! -2.5 -2 -1.5 -1 -0.5 -0.8 -0.6 -0.4 -0.2 x 10 -4 V DS (V) I D (A) VGS = -1.0V VGS = -1.5V VGS = -2.0V Assume all variables negative! VGS = -2.5V

Transistor Model for Manual Analysis

The Transistor as a Switch

The Transistor as a Switch

The Transistor as a Switch

MOS Capacitances Dynamic Behavior

Dynamic Behavior of MOS Transistor

The Gate Capacitance x L Polysilicon gate Top view Gate-bulk overlap d L Polysilicon gate Top view Gate-bulk overlap Source n + Drain W t ox n + Cross section L Gate oxide

Gate Capacitance Cutoff Triode Saturation Resistive Saturation Most important regions in digital design: saturation and cut-off

Gate Capacitance Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation

Measuring the Gate Cap

Diffusion Capacitance Bottom Side wall Channel Source N D Channel-stop implant A 1 Substrate W x j L S

Capacitances in 0.25 mm CMOS process

The Sub-Micron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic Resistances

Threshold Variations V V Low V threshold Long-channel threshold VDS L Threshold as a function of Drain-induced barrier lowering the length (for low V ) (for low L ) DS

Sub-Threshold Conduction 0.5 1 1.5 2 2.5 10 -12 -10 -8 -6 -4 -2 V GS (V) I D (A) VT Linear Exponential Quadratic The Slope Factor S is DVGS for ID2/ID1 =10 Typical values for S: 60 .. 100 mV/decade

Sub-Threshold ID vs VGS VDS from 0 to 1.0V

Sub-Threshold ID vs VDS VGS from 0 to 0.3V

Summary of MOSFET Operating Regions Strong Inversion VGS > VT Linear (Resistive) VDS < VDSAT Saturated (Constant Current) VDS  VDSAT Weak Inversion (Sub-Threshold) VGS  VT Exponential in VGS with linear VDS dependence

Parasitic Resistances

Latch-up (Effect of Parasitic Resistance)

SPICE Transistors Parameters

MAIN MOS SPICE PARAMETERS

SPICE Parameters for Parasitics

SPICE Model for NMOS and PMOS

SPICE Deck for a CMOS Inverter

SPICE Simulation Result

Future Perspectives 25 nm FINFET MOS transistor

Summary Transistor Modeling is important for CMOS circuit design (updated by IC manufacturing companies based on ongoing technologies). SPICE parameters provide a good link between manufacturer and designers. SPICE model/parameters need to be updated to reflect the behavior of the MOS in deep sub-micron technology. Recently, capacitor/inductor modeling become important for Radio-frequency (RF) designs.