Multi-Cycle CPU.

Slides:

Advertisements

Similar presentations

Pipeline Example: cycle 1 lw R10,9(R1) sub R11,R2, R3 and R12,R4, R5 or R13,R6, R7.

Advertisements

1 Datapath and Control (Multicycle datapath) CDA 3101 Discussion Section 11.

Microprocessor Design Multi-cycle Datapath Nia S. Bradley Vijay.

1 Chapter Five The Processor: Datapath and Control.

The Processor Data Path & Control Chapter 5 Part 2 - Multi-Clock Cycle Design N. Guydosh 2/29/04.

Chapter 5 The Processor: Datapath and Control Basic MIPS Architecture Homework 2 due October 28 th. Project Designs due October 28 th. Project Reports.

1 5.5 A Multicycle Implementation A single memory unit is used for both instructions and data. There is a single ALU, rather than an ALU and two adders.

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicI: Building a Multicycle Data Path and a Control Path for a Microprocessor.

CMPUT Computer Organization and Architecture II1 CMPUT229 - Fall 2003 TopicE: Building a Data Path and a Control Path for a Microprocessor José Nelson.

©UCB CS 161Computer Architecture Chapter 5 Lecture 11 Instructor: L.N. Bhuyan Adapted from notes by Dave Patterson (http.cs.berkeley.edu/~patterson)

Preparation for Midterm Binary Data Storage (integer, char, float pt) and Operations, Logic, Flip Flops, Switch Debouncing, Timing, Synchronous / Asynchronous.

ENEE350 Ankur Srivastava University of Maryland, College Park Based on Slides from Mary Jane Irwin ( )

331 W10.1Spring :332:331 Computer Architecture and Assembly Language Spring 2005 Week 10 Building a Multi-Cycle Datapath [Adapted from Dave Patterson’s.

CSE431 L05 Basic MIPS Architecture.1Irwin, PSU, 2005 CSE 431 Computer Architecture Fall 2005 Lecture 05: Basic MIPS Architecture Review Mary Jane Irwin.

Dr. Iyad F. Jafar Basic MIPS Architecture: Multi-Cycle Datapath and Control.

CMPE 421 Advanced Computer Architecture Supplementary material for Pipelining PART1.

Datapath and Control: MultiCycle Implementation. Performance of Single Cycle Machines °Assume following operation times: Memory units : 200 ps ALU and.

CPE232 Basic MIPS Architecture1 Computer Organization Multi-cycle Approach Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides

1 CS/COE0447 Computer Organization & Assembly Language Multi-Cycle Execution.

1 Processor: Datapath and Control Single cycle processor –Datapath and Control Multicycle processor –Datapath and Control Microprogramming –Vertical and.

LECTURE 6 Multi-Cycle Datapath and Control. SINGLE-CYCLE IMPLEMENTATION As we’ve seen, single-cycle implementation, although easy to implement, could.

ECE-C355 Computer Structures Winter 2008 The MIPS Datapath Slides have been adapted from Prof. Mary Jane Irwin ( )

Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data.

Fall 2015, Sep ELEC / Lecture 5 1 ELEC / Computer Architecture and Design Fall 2015 Datapath and Control (Chapter.

PC Instruction Memory Address Instr. [31-0] 4 Fig 4.6 p 309 Instruction Fetch.

Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data.

Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data.

RegDst 1: RegFile destination No. for the WR Reg. comes from rd field. 0: RegFile destination No. for the WR Reg. comes from rt field.

Adapted from Computer Organization and Design, Patterson & Hennessy, UCB ECE232: Hardware Organization and Design Part 10: Control Design

Chapter 4 From: Dr. Iyad F. Jafar Basic MIPS Architecture: Multi-Cycle Datapath and Control.

Computer Architecture Lecture 6.  Our implementation of the MIPS is simplified memory-reference instructions: lw, sw arithmetic-logical instructions:

Design a MIPS Processor (II)

Access the Instruction from Memory

Multi-Cycle Datapath and Control

Chapter 5: A Multi-Cycle CPU.

Single Cycle CPU.

Computer Architecture

IT 251 Computer Organization and Architecture

/ Computer Architecture and Design

ECE/CS 552: Multicycle Data Path

Systems Architecture I

Extensions to the Multicycle CPU

Single Cycle Processor

D.4 Finite State Diagram for the Multi-cycle processor

Multi-Cycle CPU.

Basic MIPS Architecture

Chapter Five The Processor: Datapath and Control

The Multicycle Implementation

CSCI206 - Computer Organization & Programming

Vishwani D. Agrawal James J. Danaher Professor

Computer Organization Ellen Walker Hiram College

Chapter Five The Processor: Datapath and Control

The Multicycle Implementation

Systems Architecture I

The Processor Lecture 3.2: Building a Datapath with Control

Vishwani D. Agrawal James J. Danaher Professor

COSC 2021: Computer Organization Instructor: Dr. Amir Asif

Processor: Multi-Cycle Datapath & Control

Multi-Cycle Datapath Lecture notes from MKP, H. H. Lee and S. Yalamanchili.

Chapter Four The Processor: Datapath and Control

Control Unit for Multiple Cycle Implementation

5.5 A Multicycle Implementation

Processor Design Datapath and Design.

MIPS processor continued

Systems Architecture I

Control Unit for Multiple Cycle Implementation

FloorPlan for Multicycle MIPS

Alternative datapath (book): Multiple Cycle Datapath

The Processor: Datapath & Control.

Processor: Datapath and Control

Presentation transcript:

Multi-Cycle CPU

Multi-Cycle CPU Combine Functional Units Reuse for different phases of instructions One ALU for PC increment Branch target computation Address computation for memory access R-Type instruction execution One memory unit for both instructions and data Multiple but Shorter Clock Cycles Different instructions take different number of cycles Average CPI times cycle time gives better performance

F A D A B B E C PCWrite Mem Read Mem Write IRWrite RegWrite ALUOp PC To Control 31-21 0 M 1 U X PCWrite F Zero Mem Read Mem Write PC A D IRWrite RegWrite 0 M U 1 X 0 M U 1 X 5-9 Read/Write Addr IR Read Reg 1 Read Data 1 A 16-20 0 M U 1 X B A L U ALU Out Memory Read Reg 2 Registers 0 M 1 U 2 X 3 Read Data 2 B Mem Data Write Reg 4 Write Data 0-4 Write Data E C 0 M U 1 X Mem Data Reg Sign Ext Shift Left 2 0-31 ALU Ctrl 21-31 ALUOp

Instruction Fetch/PC Increment To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr IR Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg Sign Ext Shift Left 2 15-0 ALU Ctrl 5-0 ALUOp ADD Instruction Fetch/PC Increment

Instruction Decode/Register Fetch/Branch Target To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory IR B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Decode/Register Fetch/Branch Target

Branch Completion (Branch Taken) PCWriteCond To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp SUB Branch Completion (Branch Taken)

Instruction Fetch after Branch Completion To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Fetch after Branch Completion

Instruction Decode/Register Fetch/Branch Target To Control 31-26 1 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Decode/Register Fetch/Branch Target

R-Type Instruction Execution To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp Function R-Type Instruction Execution

R-Type Instruction Write Back To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp R-Type Instruction Write Back

Instruction Fetch After R-Type To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Fetch After R-Type

Instruction Decode/Register Fetch/Branch Target To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Decode/Register Fetch/Branch Target

Address Computation (lw or sw) To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Address Computation (lw or sw)

Memory Access for lw F A D A B B C E PCWrite Mem Read Mem Write To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp Memory Access for lw

Write Back for lw F A D A B B C E PCWrite Mem Read Mem Write IRWrite To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp Write Back for lw

Instruction Fetch after lw To Control 31-26 1 PCWrite F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Fetch after lw

F A D A B B C E PCWrite Mem Read Mem Write IRWrite RegWrite ALUOp PC To Control 31-26 1 PCWrite F Zero Mem Read Mem Write PC A D IRWrite RegWrite 1 1 25-21 Read/Write Addr IR Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg Sign Ext Shift Left 2 15-0 ALU Ctrl 5-0 ALUOp

Control A B ALUOp PCWriteCond PCSrc PCWrite MemWrite ALUSrcA MemRead 31-26 1 PCWrite Zero MemWrite ALUSrcA MemRead PC IorD IRWrite RegDst RegWrite 1 1 25-21 Read/Write Addr IR Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data 1 ALUSrcB Mem Data Reg Sign Ext Shift Left 2 15-0 ALU Ctrl MemtoReg 5-0 ALUOp

Control Lines PCWriteCond Write PC conditionally on branch PCWrite Write PC for increment or jump PCSrc Select source for writing to PC IorD Select address for memory read/write MemRead Read from memory (instruction or data) MemWrite Write to memory (store word) IRWrite Write to Instruction Register

Control Lines MemtoReg Select memory or ALUOut to write to register RegDst Select field to select destination register RegWrite Write to selected register ALUSrcA Select source for upper ALU input ALUSrcB Select source for lower ALU input ALUOp Select ALU operation or set to function code: 00 = Add, O1 = Subtract, 10 = use funct field (bits 0-5)

Clock Cycles 1. Instruction Fetch, PC Increment 2. Instruction Decode, Register Fetch, Branch Target Computation 3. R-type Execution or Memory Address Computation or Branch Completion 4. R-type Write Back or Memory Access 5. Memory write back

Control Overview Instruction Fetch Instruction Decode Start Memory Access R-type Cond Branch Uncond Branch

Control: Finite State Machine Instruction Fetch 0 Instruction Decode 1 MemRead IorD = 0 IRWrite ALUSrcA = 0 ALUSrcB = 01 ALUOp = 00 PCSrc = 00 PCWrite ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Start ldur or stur R-type cbz b Memory Access FSM Cond Branch FSM Branch FSM R-type FSM

Memory Access FSM Memory Address Comp 2 From State 1 lw or sw Memory ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Memory Access lw 3 ldur stur MemRead IorD = 1 MemWrite IorD = 1 Memory Access sw 5 Write Back 4 RegWrite MemToReg = 1 RegDst = 0 To State 0

R-type FSM From State 1 R-type Execution 6 Write Back 7 To State 0 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 Execution 6 RegDst = 1 RegWrite MemtoReg = 0 Write Back 7 To State 0

Conditional Branch FSM From State 1 cbz ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSrc = 1 Branch Completion 8 To State 0

(Unconditional) Branch FSM From State 1 cbz ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWrite PCSrc = 1 Branch Completion 8 To State 0

Complete Finite State Machine Instruction Fetch 0 MemRead IorD = 0 IRWrite ALUSrcA = 0 ALUSrcB = 01 ALUOp = 00 PCSrc = 00 PCWrite Instruction Decode 1 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Start ldur or stur R-type b cbz ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Unconditional Branch Completion 9 Memory Address Comp 2 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 Execution 6 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWrite PCSrc = 1 ldur stur Memory Access ldur 3 MemRead IorD = 1 Conditional Branch Completion 8 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSrc = 1 MemWrite IorD = 1 RegDst = 1 RegWrite MemtoReg = 0 Memory Access stur 5 Write Back 7 RegWrite MemToReg = 1 RegDst = 0 Write Back 4

FSM Implementation as PLA Opcode from IR PLA Clock State Register PCWrite ALUOp PCWriteCond ALUSrcB PCSrc IorD ALUSrcA MemRead RegWrite MemWrite RegDst IRWrite MemtoReg