Lecture 13 State Machines / ROMs CSCE 211 Digital Design Lecture 13 State Machines / ROMs Topics Shift Registers State Machines Design Read only Memories (ROMs) Overview Field Programmable Gate Arrays Readings: 8.5, 9.1 November 4 or 9, 2015

Overview Last Time New Next Time: Lecture 14 State Machines Characteristic Tables of Flip-flops Excitation Tables of Flip-flops General State Machine Design New State Machines Shift Registers HW Read only Memories (ROMs) Overview Field Programmable Gate Arrays Next Time: Test 2 : Thursday ???? HW: Next : Class: Programmable Array Logic (PALs)

Tables for State Machines Current State Inputs Next State Flip-flop inputs Outputs A B C L R H TA TB DC X Y Z 1 … How many rows?

Simple Coke Machine Design Draw the state diagram for the machine, e.g. Coke machine. Map the state diagram to a state table. Choose a set of state variables and assign combinations of variables to states. Build the Transition/output table. Specify which type of flip-flops will be used for each state variable. Give the excitation table. Give logic Diagrams for flip-flop inputs. Give logic diagrams for the outputs.

State Diagram for Simple Coke Machine Restrictions Only accepts quarters Only has cokes Assume clocked change state only when cp=1 Steps in State Machine Design Draw state diagram Map to state table Choose/Assign state variables Build Transition/output table … State Diagram s0 start q=0 q=1 s2 s1 25¢ q=1 50¢ dispense coke

State Table for Coke Machine Steps in State Machine Design Draw state diagram Map to state table Choose/Assign state variables State Diagram s0 start q=0 q=1 Current State Inputs q Next State s2 s1 25¢ q=1 S0 1 S1 S2 50¢ dispense coke

Choose/Assign State Variables for Coke Machine Steps in State Machine Design Draw state diagram Map to state table Choose/Assign state variables Three states  how many variables necessary to encode? Choose variables, say A, B Assign values S0 =A B = 00 S1 =A B = 01 S2 =A B = 11 Current State Inputs Next State A B q 1 X

Build the Transition/output table for Coke Machine Current State Inputs Next State Dispense on rising edge or just once per CP Next step is to choose the flip-flop type Let’s use D flip-flops Output Dispense Disp X? 1 A B q 1 X

Give the excitation table Using D flip-flops Current State Inputs Next State Outputs Flip-flop inputs A B q Dispense DA DB 1 X

Logic Diagrams Karnaugh maps for each column Output: Dispense = AB 00 01 11 10 q Karnaugh maps for each column Output: Dispense = Flip-flop inputs DA DB 1 Disp q AB 00 01 11 10 q 1 DA q AB 00 01 11 10 q 1 DB q

Logic Diagrams

Shift Left Register t L SI A4 A3 A2 A1 A0 SO 1 2 3 4 5 6 7 Parallel output A4 A3 A2 A1 A0 t L SI A4 A3 A2 A1 A0 SO 1 =A4* 2 3 4 5 6 7 Serial Output Serial Input

Shift Left Logic Design

Parallel Load Shift Registers

Continuing Examples (CE) CE7. A Mealy system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times. CE8. A Moore system with one input x and one output z, the output of which is 1 iff three consecutive 0 inputs occurred more recently than three consecutive 1 inputs. CE9. A system with no inputs and three outputs, that represent a number from 0 to 7, such that the output cycles through the sequence 0 3 2 4 1 5 7 and repeat on consecutive clock inputs. CE10. A system with two inputs, x1 and x2, and three outputs, z1, z2, and z3, that represent a number from 0 to 7, such that the output counts up if x1 = 0 and down if x1 = 1, and recycles if x2 = 0 and saturates if x2 = 1. Thus, the following output sequences might be seen x1 = 0, x2 = 0: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 … x1 = 0, x2 = 1: 0 1 2 3 4 5 6 7 7 7 7 7 7 7 7 7 … x1 = 1, x2 = 0: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 … x1 = 1, x2 = 1: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 … (Of course, x1, and x2 may change at some point so that the output would switch from one sequence to another.)

Step 1: From a word description, determine what needs to be stored in memory, that is, what are the possible states. Step 2: If necessary, code the inputs and outputs in binary. Step 3: Derive a state table or state diagram to describe the behavior of the system. Step 4: Use state reduction techniques (see Chapter 7) to find a state table that produces the same input/output behavior, but has fewer states. Step 5: Choose a state assignment, that is, code the states in binary. Step 6: Choose a flip flop type and derive the flip flop input maps or tables. Step 7: Produce the logic equation and draw a block diagram (as in the case of combinational systems).

D1 = x q2 + x q1 D2 = x q´2 + x q1

J1 = xq2 K1 = x´ z = q1q2 J2 = x K2 = x´ + q´1

S1 = xq2 R1 = x´ z = q1q2 S2 = xq´2 R2 = x´ + q´1q2

T1 = x´q1 + xq´1q2 T2 = x´q2 + xq´2 + xq´1q2 z = q1q2

z = x´ + q1q2 D1 = x´ + q´1 + q´2 D2 = xq´2 + xq´2 J1= 1 K1 = xq2 J2 = x´ K2 = x´

DA = xAC´ + xBC DB = x´A + x´B + x´C DC = x´A + x´B + x´C´ + AC´ z = A + BC JD = KD = CBA JC = KC = BA JB = KB = A JA = KA = 1

JA = KA = 1 JB = KB = x´A + xA´ JC = KC = x´BA + xB´A´

0, 3, 2, 4, 1, 5, 7, and repeat

D1 = q´2q3 + q2q´3 D2 = q´1q´2q´3 + q´1q2q3 + q1q´2q3 D3 = q´2

q1 = 1, q2 = 1, and q3 = 0 D1 = q´2q3 + q2q´3 = 00 + 11 = 1 D2 = q´1q´2q´3 + q´1q2q3 + q1q´2q3 = 001 + 011 + 100 = 0 D3 = q´2 = 0

CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times.

A none, that is, the last input was 0 B one C two D three or more

CE7. A system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times. CE7#. A Mealy system with one input x and one output z such that z = 1 iff x has been 1 for three consecutive clock times.

A none, that is, the last input was 0 B one C two or more

Read Only Memory Functionality

3-Input 4-Output ROM OR D0 A0 OR D1 A0 3x8 decoder A1 OR D2 A2 OR D3

Construction of a 2 x n ROM d0 d1 A0 2x4 decoder d2 A1 d3 Zap some connections during construction Denoted “x” … Y0 Y1 Y2 Yn-1

2x4 Decoder with Output-Polarity Control Figure 9-2

Implementing Arbitrary Boolean functions with ROMs

Multipliers in ROM Figure 9-4

Fig 9-5 Logic Diagram of 8x4 diode ROM 74LS138 =1-OF-8 DECODER/ DEMULTIPLEXER

Two-Dimensional Decoding

Field Programmable Gate Arrays Xilinx Spartan-3 FPGA family. Download circuits onto the chip FPGA Field Programmable Gate array Spartan-3 FPGAs with 1 million system gates for under $12.00

Xilinx FPGA

Configurable Logic Blocks

LUTs – Look Up Tables Circuits are built in FPGA using Look Up Tables or LUTs. A lut is just a sequence of storage cells and then a collection of multiplexers select which storage cell is routed to the output,

LUT Structure (Pawel Chodowiec - Architecture of Xilinx FPGA devices)

CLB for Functions of 5 variables

Spartan -3 Starter Board

I/O Blocks