1. CS 352 Introduction to Logic Design
Lecture 7
Ahmed Ezzat
Analysis of Clocked Sequential Circuits
Ch-13

2. Outline General Models for Sequential Circuits
Analysis of Clocked Sequential Circuits
A Sequential Parity Checker
Analysis by Signal Tracing and Timing Charts
State Tables and Graphs
Construction and Interpretation of Timing Charts
General Models for Sequential Circuits
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3. Analysis of Clocked Sequential Circuits
So far we covered primitive sequential circuits (shifter, counter). They have fixed sequence of states and have no input, other than a clock.
Here we will consider sequential circuits that have additional inputs. For these circuits, output and F/F states will depend on the input sequence which is applied.
For simple circuits, given sequence of input, we can analyze/trace the circuit to determine internal states and output sequence.
For more complex circuits, it is better to construct a state graph or state table which represent the circuit behavior  determine output from the state graph/table.
The state graph/table is also useful for the design of sequential circuits.
We will also study the timing relationship between inputs, clock, and outputs.
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4. A Sequential Parity Checker (1)
Odd/even parity is a technique for error checking due to transmission noise/errors.
As an example of more complex sequential circuit s to design a parity checker for serial data
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5. A Sequential Parity Checker (2)
In the above circuit, when sequence of 0’s and 1’s is applied to the X input, the output of the circuit should be Z = 1, for odd parity circuit.
An output Z = 0 indicates an error in transmission has occurred.
Value of X is read at the active clock edge, i.e., there has to be synchronization between X input and the clock.
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6. A Sequential Parity Checker (3)
First, let us construct the state graph. We have only 2 states (S0, S1): correspond to an even and odd number of 1’s received so far.
Z = 1 whenever circuit is in state S1 or in State S0 and X = 1
Z = 0 whenever circuit is in state S0 or in State S1 and X = 1
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7. A Sequential Parity Checker (4)
Such Parity checker (2 states) can be implemented using a T F/F
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8. Analysis by Signal Tracing and Timing Charts (1)
Given sequence of inputs to a clocked sequential circuit, find the output sequence by tracing 0 and 1 signals through the circuit:
Assume all F/Fs are reset to 0
For the 1st input, determine the circuit output(s) and F/F inputs
Determine the new set of F/F states after the next active clock edge
Determine the output(s) that corresponds to the new F/F states
Repeat for each input in the given input sequence
From the above analysis construct timing chart which shows the relationship between input signal, the clock, F/F states, and output
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9. Analysis by Signal Tracing and Timing Charts (2)
Two types of clocked Sequential circuits:
Moore Machine: Output depends only on present state of F/Fs
Mealy Machine: Output depends on inputs and present state of F/Fs
Example of Moore Machine: Z = A B +
Input Sequence X = 01101
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10. Analysis by Signal Tracing and Timing Charts (3)
Output (Z) will only change when A or B changes
Initially A = B = 0, X = 0, DA =1, DB = 0  AB = 10 on 1st rising clock edge
X  1  DA = 0, DB = 1  AB = 01 on 2nd rising clock edge
X remains 1  DA = DB = 1  AB = 11 on 3rd rising clock edge
X  0  DA = 0, DB = 1  AB = 01 on 4th rising clock edge
X  1  DA = DB = 1  AB = 11 on 5th rising clock edge
() means irrelevant output
No false output happens because output can change only on F/F state changes and not when input changes X 1 A B Z
(0)
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11. Analysis by Signal Tracing and Timing Charts (4)
When the circuit is reset A = B = 0, output Z = 0. Because it is independent of input it should be ignored.
The input sequence X = 01101, and resulting output Z = 11010
In Moore circuits output which result from input sequence does not appear until after the first active clock edge  output is displaced in time relative to input sequence
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12. Analysis by Signal Tracing and Timing Charts (5)
Example of Mealy Machine:
Assume input sequence X = 10101
Changes happen on the falling active edge of the clock
Output appears shortly after input (before active clock edge), output sequence is not displaced in time w.r.t. input sequence
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13. Analysis by Signal Tracing and Timing Charts (6)
Output depends on both input and F/F states, i.e., Z may change when input changes or when F/F state change
Initially assume A = B = 0
If X = 1 (1st clock)  Z = 1  B = 1  Z = 0
If X = 0 (2nd clock)  Z = 1, JA = JB = 0 no change in state
X = 1 (3rd clock)  Z = 0, JA = KA = JB = 1
X = 0 (4th clock)  Z = 0, no state change
X = 1 (5th clock)  Z = 1, JA = KA = JB = KB = 1  returns to initial state
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14. Analysis by Signal Tracing and Timing Charts (7)
False output is indicated in parentheses
An observation for Mealy circuit is necessary: after circuit change state and before input is changed, the output may temporarily assume an incorrect value, which we call false output. This arises when the circuit assumes new state but the old input associated with the previous state is till present
These false outputs are often called glitches and spikes. Spikes should be ignored, and output should be read just before the falling clock edge
Z =  spikes can be eliminated if X changes only on falling clock edge X 1 A B Z
1(0)
0(1)
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15. State Tables and Graphs (1)
We analyzed clocked sequential circuits by signal tracing and constructing of timing charts  suitable for small circuits and short input sequence
Constructing a state table and graph provides systematic approach and leads to a general synthesis procedure for sequential circuits
State table specifies next state and output in terms of its present state and input
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16. State Tables and Graphs (2)
Procedure to constructing a state table:
Determine the F/F input and output equation from the circuit
Derive the next-state equation for each F/F from its input equations using one of the following relations 
Plot next state map for each F/F
Combine these maps to form the state table – next state of F/F based on present state and current inputs is referred to transition table
D F/F
Q+ = D
D-CE F/F
Q+ = D.CE + Q.CE’
T F/F
Q+ = T Q
S-R F/F
Q+ = S + R’Q
J-K F/F
Q+ = JQ’ + K’Q +
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17. State Tables and Graphs (3)
Revisit Moore Machine:
Input and Output equations: DA = X B’ DB = X + A Z = A B
Next state equation for the F/F are: A+ = X B’ B+ = X + A
Corresponding maps are: + + +
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18. State Tables and Graphs (4)
Combining the above 2 maps yields the following transition table
Using the above left table, we can construct the timing chart for any given input sequence.
Initially AB =00, X = 0  Z = 0 and A+B+ = 10  after rising clock edge, F/F AB = 10  Z = 1. Next input X =1 so A+B+ = 01  after rising clock edge F/F AB = 10, etc.
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19. State Tables and Graphs (5)
If we are not interested in internal state, we replace the combination of F/F states with a single symbol that represent the circuit state. For example, replace AB = 00 with S0, 01 with S1, 10 with S2, 11 with S3. This yields the right table, last page, which can be represented by the following state graph. Each node represents a state of the circuit, and corresponding output is placed in the lower half of the circle. Arcs between nodes are labeled with value of X which will cause state transition
Homework: study constructing state table and graph for Mealy Machine
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20. State Tables and Graphs (6)
Example Serial Adder: Adds two n-bit binary numbers X = xn-….x1x0 and Y = yn-1 … y1y0. The adder adds 2-bits at a time. Initially, it adds x0 and y0  s0 and c0. c0 is saved in a D F/F and next clock the full adder will add x1, y1, c0  s1 and c1. xi yi ci
ci+1 Si 1
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21. State Tables and Graphs (7)
For adding X = 10011, Y =  S = and final carry = 0
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22. State Tables and Graphs (8)
The state graph constructed from the truth table (page 20) is as follows:
S0 and S1 represent a carry (Ci) of 0 and 1
Ci is present state, Ci+1 is next state
Serial adder is a Mealy machine with inputs xi, yi and output si
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23. State Tables and Graphs (9) Construction and Interpretation of Timing Charts
Constructing and Interpretation of timing charts:
State change happens only after the active edge of the clock
Input needs to be stable just before and after the active clock edge
Moore circuits: output can change only when the state change
Mealy circuits: output can change when the input changes as well when state changes
False output can happen between the time the state changes and the time input is changed
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24. State Tables and Graphs (10) Construction and Interpretation of Timing Charts
With Mealy state table, constructing timing chart follow this procedure:
a) For 1st input, read present output and plot it
b) Read next state and plot it following the active edge
c) Go to the row in the table that corresponds to next state and read output under the old input column and plot it (may be false output)
d) Change to next input and repeat steps a  c
For Mealy circuits, the best time to read output is just before the active edge where output is always correct at that time
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25. General Models for Sequential Circuits (1)
A sequential circuit can be divided into 2 parts:
F/F which serves as memory for the circuit
Combinational logic which realizes input to F/F and output functions
The combinational logic can be implemented using gates, ROM, or PLA
This Mealy circuit has m inputs, n outputs, and k clocked D F/Fs.
The combinational circuit realizes n outputs and k next-state functions which serve as input to the D F/Fs
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26. General Models for Sequential Circuits (2)
Z1 = f1(X1, X2, …. Xm, Q1, Q2, …. Qk) Z2 = f2(X1, X2, …. Xm, Q1, Q2, …. Qk)
Zn = fn(X1, X2, …. Xm, Q1, Q2, …. Qk)
Q1+ = D1 = g1(X1, X2, …. Xm, Q1, Q2, …. Qk) Q2+ = D2 = g2(X1, X2, …. Xm, Q1, Q2, …. Qk) .
Qk+ = Dk = gk(X1, X2, …. Xm, Q1, Q2, …. Qk)
n output functions
K next-state functions
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27. General Models for Sequential Circuits (3)
When input is applied, the combinational sub-circuit generates output (Z1, Z2, …, Zn) and F/F inputs (D1, D2, …, Dk)
Clock is applied and the F/Fs change state appropriately
This process is repeated for each set of inputs
At any point in time, F/F outputs represent the circuit state (Q1, Q2, …, Qk)
Qi’s feed back into the combinational circuit, which generates F/F input using Qi’s and X inputs (Di = Qi+)
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28. END
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