Sequential Programmable Devices

Slides:



Advertisements
Similar presentations
Lecture 11-1 FPGA We have finished combinational circuits, and learned registers. Now are ready to see the inside of an FPGA.
Advertisements

Programmable Logic Devices
©2004 Brooks/Cole FIGURES FOR CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES Click the mouse to move to the next page. Use the ESC key.
Implementing Logic Gates and Circuits Discussion D5.1.
Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.
Multiplexers, Decoders, and Programmable Logic Devices
ECE 331 – Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #16) The slides included herein were taken.
Programmable Array Logic (PAL) Fixed OR array programmable AND array Fixed OR array programmable AND array Easy to program Easy to program Poor flexibility.
Introduction to FPGA’s FPGA (Field Programmable Gate Array) –ASIC chips provide the highest performance, but can only perform the function they were designed.
EET 252 Unit 5 Programmable Logic: FPGAs & HDLs  Read Floyd, Sections 11-5 to  Study Unit 5 e-Lesson.  Do Lab #5.  Lab #5a due next week. 
Lecture 2: Field Programmable Gate Arrays September 13, 2004 ECE 697F Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays.
DSD Presentation Introduction of Actel FPGA. page 22015/9/11 Presentation Outline  Overview  Actel FPGA Characteristic  Actel FPGA Architecture  Actel.
Unit 9 Multiplexers, Decoders, and Programmable Logic Devices
© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Fundamentals Tenth Edition Floyd.
Electronics in High Energy Physics Introduction to Electronics in HEP Field Programmable Gate Arrays Part 1 based on the lecture of S.Haas.
PLD (Programmable Logic Device) Wednesday, October 07, ARINDAM CHAKRABORTY LECTURER,DEPT. OF ECE INSTITUTE OF ENGINEERING & MANAGEMENT.
CPLD (Complex Programmable Logic Device)
Memory and Programmable Logic Memory device: Device to which binary information is transferred for storage, and from which information is available for.
J. Christiansen, CERN - EP/MIC
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR FPGA Fabric n Elements of an FPGA fabric –Logic element –Placement –Wiring –I/O.
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n FPGA fabric architecture concepts.
Programmable Logic Devices
Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.
Sept. 2005EE37E Adv. Digital Electronics Lesson 1 CPLDs and FPGAs: Technology and Design Features.
Field Programmable Gate Arrays (FPGAs) An Enabling Technology.
Programmable Logic Devices
ESS | FPGA for Dummies | | Maurizio Donna FPGA for Dummies Basic FPGA architecture.
Basic Logic Functions Chapter 2 Subject: Digital System Year: 2009.
Programmable Logic Devices. Principle of Operation: Example: X = A.B + A’.B’ requires that fuses f1 and f4 to be “blown”.
Delivered by.. Love Jain p08ec907. Design Styles  Full-custom  Cell-based  Gate array  Programmable logic Field programmable gate array (FPGA)
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n FPGA fabric architecture concepts.
FPGA 상명대학교 소프트웨어학부 2007년 1학기.
Gunjeet Kaur Dronacharya Group of Institutions. Outline Introduction Random-Access Memory Memory Decoding Error Detection and Correction Programmable.
Programmable Logic Devices
Field Programmable Gate Arrays
This chapter in the book includes: Objectives Study Guide
Issues in FPGA Technologies
ETE Digital Electronics
Digital Design Lecture 14
Sequential Logic Design
Reconfigurable Architectures
This chapter in the book includes: Objectives Study Guide
Complex Programmable Logic Device (CPLD) Architecture and Its Applications
Give qualifications of instructors: DAP
Each I/O pin may be configured as either input or output.
XILINX FPGAs Xilinx lunched first commercial FPGA XC2000 in 1985
Overview The Design Space Programmable Implementation Technologies
From Silicon to Microelectronics Yahya Lakys EE & CE 200 Fall 2014
This chapter in the book includes: Objectives Study Guide
ELEN 468 Advanced Logic Design
Programmable Logic Devices: CPLDs and FPGAs with VHDL Design
These chips are operates at 50MHz clock frequency.
We will be studying the architecture of XC3000.
Chapter 13 – Programmable Logic Device Architectures
CPE 528: Session #12 Department of Electrical and Computer Engineering University of Alabama in Huntsville.
حافظه و منطق قابل برنامه ریزی
The architecture of PAL16R8
Programmable Electrically Erasable Logic Devices (PEEL)
حافظه و منطق قابل برنامه ریزی
Programmable Logic.
Introduction to Programmable Logic Devices
Digital Fundamentals Tenth Edition Floyd Chapter 11.
Programmable Logic- How do they do that?
EEE2243 Digital System Design Chapter 9: Advanced Topic: Physical Implementation by Muhazam Mustapha extracted from Frank Vahid’s slides, May 2012.
PROGRAMMABLE LOGIC DEVICES (PLD) UNIT-IV
FIGURE 5-1 MOS Transistor, Symbols, and Switch Models
Physical Implementation
Implementing Logic Gates and Circuits
Programmable logic and FPGA
Presentation transcript:

Sequential Programmable Devices

Sequential Programmable Devices The combinational PLD consist only gates Sequential Programmable Devices includes both gates and filp-flop Type of sequential Programmable Devices: Sequential (simple) programmable logic device (SPLD) Complex programmable logic device (CPLD) Field programmable gate array (FPGA)

SPLD SPLD: consist PAL and D flip-flop Each section in SPLD is called Microcell

SPLD The basic microcell logic A typical SPLD has from 8 to 10 AND-OR array Edge-triggered D flip-flop Three-state buffer(inverter) A typical SPLD has from 8 to 10 macrocells within one IC package

CPLD CPLD is a collection of individual PLDs on a single integrated circuit Each PLD typically contains from 8 to 16 macroceIls CPLD has two levels of programmability: Each PLD block Interconnections between the PLDs Each I/0 pin is driven by a three state buffer and can be programmed to act as input or output

FPGA FPGA is a VLSI circuit that can be programmed at the user's location Consist of: hundreds or thousands of logic blocks Programmable interconnection programmable input and output blocks

Logic block Used to implement any boolean function Consist of: Look up table (LUTs) , Multiplexers , PLD blocks or NAND gates (implemented logic function) Multiplexers (select 1 of N inputs) Flip-flop, Registers. Clocked Storage elements.

Interconnection (Routing) FPGAs have 3 programmable routing resources : Vertical and horizontal routing channels Connection boxes connect input and output pins of the CLBs to wires of the vertical or the horizontal routing channels Switch boxes connect wire segments in the horizontal and vertical channels Technology of connection Static RAM Anti fuse EPROM EEPROM

I/O blocks They allow the pins of the FPGA chip to function either as input pins, output pins or input/output pins Programmable I/O

Circuit compilation

Major FPGA Vendors SRAM-based FPGAs Flash & antifuse FPGAs Xilinx, Inc. Altera Corp. Atmel Lattice Semiconductor Flash & antifuse FPGAs Actel Corp. Quick Logic Corp.

Altera DE2-70