Digital Integrated Circuits A Design Perspective EE141 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices

Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-sub-micron effects Future trends

The Diode Mostly occurring as parasitic element in Digital ICs n p B A SiO 2 Al Cross-section of pn -junction in an IC process One-dimensional representation diode symbol Mostly occurring as parasitic element in Digital ICs

Diode Current --current increases by a factor of 10 for every extra 60 mV of forward bias

Forward Bias

Reverse Bias

Models for Manual Analysis VDon depends upon IS, a value of 0.7 V is typically assumed. IS is proportional to the area of the diode, and a function of the doping levels and widths of the neutral regions 10-17 A/um2.

Junction Capacitance/ Depletion layer capacitance The capacitance decreases with an increasing reverse bias

Secondary Effects Avalanche Breakdown 0.1 ) A ( I D –0.1 –25.0 –15.0 –5.0 5.0 V (V) D Avalanche Breakdown --The value of Ecrit is approximately 2 *105 V/cm

Diode Model

SPICE Parameters

What is a Transistor? A Switch! |V GS | An MOS Transistor

The MOS Transistor Polysilicon Aluminum

MOS Transistors -Types and Symbols G G S S NMOS Enhancement NMOS Depletion D D G G B S S NMOS with PMOS Enhancement Bulk Contact

Threshold Voltage: Concept EE141 Consider first the case where VGS = 0 and drain, source, and bulk are connected to ground. The drain and source are connected by back-to-back pn-junctions (substrate-source and substrate-drain). Under the mentioned conditions, both junctions have a 0 V bias and can be considered off, which results in an extremely high resistance between drain and source. Assume now that a positive voltage is applied to the gate (with respect to the source), as shown in Figure 3.13. The gate and substrate form the plates of a capacitor with the gate oxide as the dielectric. The positive gate voltage causes positive charge to accumulate on the gate electrode and negative charge on the substrate side. The latter manifests itself initially by repelling mobile holes. Hence, a depletion region is formed below the gate. This depletion region is similar to the one occurring in a pn-junction diode. As the gate voltage increases, the potential at the silicon surface at some point reaches a critical value, where the semiconductor surface inverts to n-type material. This point marks the onset of a phenomenon known as strong inversion and occurs at a voltage equal to twice the Fermi Potential (Eq. (3.16)) (fF ª -0.3 V for typical p-type silicon sub- strates) Further increases in the gate voltage produce no further changes in the depletion- layer width, but result in additional electrons in the thin inversion layer directly under the oxide. These are drawn into the inversion layer from the heavily doped n+ source region. Hence, a continuous n-type channel is formed between the source and drain regions, the conductivity of which is modulated by the gate-source voltage.

EE141 The Threshold Voltage

The Body Effect

Current-Voltage Relations A good transistor 0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Resistive Saturation VDS = VGS - VT Quadratic Relationship

Transistor in Linear

Transistor in Saturation EE141 Transistor in Saturation Pinch-off PINCH-OFF: Now, let's see how the above conclusion affects the charge in the inversion layer. Recall that this charge is accumulated under the Gate due to Gate-to-Substrate voltage (yes, Substrate, not Source. The reason we usually use VGS in our calculations is because we assume that the Substrate and the Source are connected to the same potential). Now, if the potential change along the channel when we apply VDS, the Gate-to-Substrate voltage also change along the channel, which means that the induced charge density will vary along the channel. When we apply VDSAT=VGS-VT to the Drain, the effective Gate-to-Substrate voltage near the Drain will become: VGSeff_D=VGS-VDSAT=VT. It means that near the Drain the Gate-to-Substrate voltage is just enough to form the inversion layer. Any higher potential applied to Darin will cause this voltage to reduce below the Threshold voltage and the channel will not be formed - pinch-off occurs.

Current-Voltage Relations Long-Channel Device

A model for manual analysis

Current-Voltage Relations The Deep-Submicron Era -4 V DS (V) 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Early Saturation Linear Relationship

Channel Length Modulation

Velocity Saturation u ( m / s ) u = 10 x = 1.5 x (V/µm) EE141 Velocity Saturation u n ( m / s ) Scattering, collisions u sat = 10 5 Constant velocity Constant mobility (slope = µ) The behavior of transistors with very short channel lengths (called short-channel devices) deviates considerably from the resistive and saturated models, presented in the previous paragraphs. The main culprit for this deficiency is the velocity saturation effect. Eq. (3.23) states that the velocity of the carriers is proportional to the electrical field, independent of the value of that field. In other words, the carrier mobility is a constant. However, at high field strengths, the carriers fail to follow this linear model. In fact, when the electrical field along the channel reaches a critical value xc, the velocity of the carriers tends to saturate due to scattering effects (collisions suffered by the carriers). For p-type silicon, the critical field at which electron saturation occurs is around 1.5 ¥ 106 V/m (or 1.5 V/mm), and the saturation velocity usat approximately equals 105 m/s. This means that in an NMOS device with a channel length of 1 mm, only a couple of volts between drain and source are needed to reach the saturation point. This condition is easily met in current short-channel devices. Holes in a n-type silicon saturate at the same veloc- ity, although a higher electrical field is needed to achieve saturation. Velocity-saturation effects are hence less pronounced in PMOS transistors. x c = 1.5 x (V/µm)

Perspective I V Long-channel device squared V = V Short-channel device GS DD Short-channel device linear V V - V V DSAT GS T DS

Mobility Degradation

ID versus VGS linear quadratic quadratic Long Channel Short Channel 0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V GS (V) I D (A) 0.5 1 1.5 2 2.5 x 10 -4 V GS (V) I D (A) linear quadratic quadratic Long Channel Short Channel * Subthreshold conduction

Subthreshold Slope

ID versus VDS Resistive Saturation VDS = VGS - VT 0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Resistive Saturation VDS = VGS - VT -4 V DS (V) 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Long Channel (Ld=10um) Short Channel(Ld=0.25 um)

A PMOS Transistor Assume all variables negative! -2.5 -2 -1.5 -1 -0.5 -0.8 -0.6 -0.4 -0.2 x 10 -4 V DS (V) I D (A) VGS = -1.0V VGS = -1.5V VGS = -2.0V Assume all variables negative! VGS = -2.5V

Transistor Model for Manual Analysis

A similar result can be obtained by just averaging the values of the resistance at the end points (and simplifying the result using a Taylor expansion):

MOS Capacitances Dynamic Behavior

Dynamic Behavior of MOS Transistor

Dynamic Behavior of MOS Transistor The capacitances originate from three sources: the basic MOS structure, the channel charge, and the depletion regions of the reverse-biased pn-junctions of drain and source. Aside from the MOS structure capacitances, all capacitors are nonlinear and vary with the applied voltage, which makes their analysis hard.

MOS Structure Capacitances : The Gate Capacitance EE141 MOS Structure Capacitances : The Gate Capacitance x d L Polysilicon gate Top view Gate-bulk overlap Source n + Drain W it is useful to have Cox as large as possible The gate of the MOS transistor is isolated from the conducting channel by the gate oxide that has a capacitance per unit area equal to Cox = eox / tox. We learned earlier that from a I- V perspective it is useful to have Cox as large as possible, or to keep the oxide thickness very thin. The total value of this capacitance is called the gate capacitance Cg and can be decomposed into two elements, each with a different behavior. Obviously, one part of Cg contributes to the channel charge, and is discussed in a subsequent section. Another part is solely due to the topological structure of the transistor. This component is the subject of the remainder of this section. Consider the transistor structure of Figure 3.28. Ideally, the source and drain diffu- sion should end right at the edge of the gate oxide. In reality, both source and drain tend to extend somewhat below the oxide by an amount xd, called the lateral diffusion. Hence, the effective channel of the transistor L becomes shorter than the drawn length Ld (or the length the transistor was originally designed for) by a factor of DL = 2xd. It also gives rise to a parasitic capacitance between gate and source (drain) that is called the overlap capac- itance. This capacitance is strictly linear and has a fixed value. lateral diffusion t ox n + Cross section L Gate oxide

Gate Capacitance Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off The gate-capacitance components are nonlinear and varying with the operating voltages. To make a first-order analysis possible, we will use a simplified model with a constant capacitance value in each region of operation.

Gate Capacitance [Dally98] Capacitance as a function of VGS When increasing VGS, a depletion region forms under the gate. This seemingly causes the thickness of the gate dielectric to increase, which means a reduction in capacitance. Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation The large fluctuation of the channel capacitance around VGS=VT is worth remembering. A designer looking for a well-behaved linear capacitance should avoid operation in this region. [Dally98]

Measuring the Gate Cap

Assignment-4 - Find the gate capacitances of NMOS and PMOS devices used in the inverter of Assignment-1 using SPICE simulations. - Obtain the inverter characteristics by incorporating these capacitances in the simulation. Report any differences.

Diffusion/Junction Capacitance - bottom-plate junction - side-wall junction

Channel-stop implant Channel-stop implant required to prevent parasitic mosfets. Prevents conduction between unrelated transistor sources and drains (and wells). Two n+ regions and the FOX from a transistor. FOX is thick, therefore transistor has a large Vth. Nonetheless, a sufficiently positive potential on the interconnect line will turn on the transistor slightly (causing a leakage path). Channel-stop implant raises Vth of parasitic transistor to a very large value.

Since all these capacitances are small-signal capacitances, we normally linearize them and use average capacitances

Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest

Junction Capacitance

Exercise

Capacitances in 0.25 mm CMOS process

The Sub-Micron MOS Transistor

Threshold Variations V V Low V threshold Long-channel threshold VDS L EE141 Threshold Variations V T V T Low V threshold Long-channel threshold DS VDS DIBL: Another short channel effect is that there is a lower drain-source voltage needed for "punch through". This is where the mosfet will start conducting even if there is no gate-source voltage. This happens because the depletion region at the p-n junctions of the source and body, and drain and body both become larger as the drain-source voltage increases. At a certain drain-source voltage these depletion regions will merge together and any electron injected into this region can travel through the mosfet. This means that when this happens the current through the mosfet becomes independent of the gate-source voltage. For shorter channel devices the depletion regions will merge together sooner because they are already closer due to the fact that the drain and source are closer together. L Threshold as a function of Drain-induced barrier lowering the length (for low V ) (for low L ) DS punch-through, may cause permanent damage to the device

Hot-Carrier Effects (Trapped Oxide Charges) Tunneling, E=104 V/cm, L=1 um, Vt NMOS up, Vt NMOS down

Parasitic Resistances RD when scaling RD reduces ID RD should be small Titanium or Tungsten Silicidation Wider transistors than required Prevent by: Proper attention to layout and silcidation

Latchup The result of this effect is shorting of VDD and VSS lines proper substrate and well contacts should be there minimize Rwell and Rsub

SPICE MODELS

MAIN MOS SPICE PARAMETERS

SPICE Parameters for Parasitics

Process Variations

Scaling

Full Scaling (Constant Electrical Field Scaling) In this ideal model, voltages and dimensions are scaled by the same factor S. The goal is to keep the electrical field patterns in the scaled device identical to those in the original device. Keeping the electrical fields constant ensures the physical integrity of the device and avoids breakdown or other secondary effects. This scaling leads to greater device density (Area), higher performance (Intrinsic Delay), and reduced power consumption (P) Fixed-Voltage Scaling: In reality, full scaling is not a feasible option. First of all, to keep new devices compatible with existing components, voltages cannot be scaled arbitrarily. Having to provide for multiple supply voltages adds considerably to the cost of a system. In a velocity-saturated device, keeping the voltage constant while scaling the device dimensions does not give a performance advantage over the full-scaling model, but instead comes with a major power penalty. .

General Scaling: The supply voltages, while moving downwards, are not scaling as fast as the technology. For instance, for the technology scaling from 0.5 mm to 0.1 mm, the maximum supply-voltage only reduces from 5 V to 1.5 V. The obvious question is why not to stick to the full-scaling model, when keeping the voltage higher does not yield any convincing benefits? This departure is motivated by the following argumentation: -- Some of the intrinsic device voltages such as the silicon bandgap and the built-in junction potential, are material parameters and cannot be scaled. --The scaling potential of the transistor threshold voltage is limited. Making the threshold too low makes it difficult to turn off the device completely (cannot keep Vt too low). This is aggravated by the large process variation of the value of the threshold, even on the same wafer. Here dimensions and voltages are scaled independently

Future Perspectives While the planar FET may have reached the end of its scalable lifespan, the semiconductor industry has found an alternative approach with FinFETs; viewed by many as the best choice for next generation advanced processes. 

Future Perspectives:FINFET With advanced geometry planar FET technologies, such as 20nm, the source and the drain encroach into the channel, making it easier for leakage current to flow between them and making it very difficult to turn the transistor off completely. FinFETs are 3d structures that rise above the substrate and resemble a fin, hence the name. The 'fins' form the source and drain, effectively providing more volume than a planar transistor for the same area. The gate wraps around the fin, providing better control of the channel and allowing very little current to leak through the body when the device is in the 'off' state. This, in turn, enables the use of lower threshold voltages and results in better performance and dynamic power consumption. 

Future Perspectives:CNTFET EE141 Future Perspectives:CNTFET CNTFET CNT: Carbon Nanotube CNT properties: strength (strongest and stiffest materials yet discovered in terms of tensile strength and elastic modulus respectively [Covalent Bonding]), hardness (diamond),electrical ( electric current density of 4 × 109 A/cm2, which is more than 1,000 times greater than those of metals such as copper, where for copper interconnects current densities are limited by electromigration.), thermal (2800 °C in vacuum and about 750 °C in air), [Sudhanshu Choudhary et.al., Mod.Phys.Lett.B.Vol.28.No.2.pp.1-9,2014]