Mohamed Younis CMCS 411, Computer Architecture 1 CMSC Computer Architecture Lecture 8 Hardware Design Languages February 21, CMSC411.htm

Mohamed Younis CMCS 411, Computer Architecture 2 Lecture’s Overview q Previous Lecture: Constructing an Arithmetic Logic Unit (Different blocks and gluing them together) Scaling bit operations to word sizes (Ripple carry adder, MIPS ALU) Optimization for carry handling (Measuring performance, Carry lookahead) q This Lecture: Design phases Hardware design languages (HDL) The “eSim” a simple and miniaturized HDL

Mohamed Younis CMCS 411, Computer Architecture 3 Abstraction Hierarchy of Digital Design q Structural domain: Components are described in terms of an interconnection of more primitive components q Behavior domain: Components are described by defining the their input/output responses by means of a procedure Digital designers often employ abstraction hierarchy, which can be expressed in two domains:

Mohamed Younis CMCS 411, Computer Architecture 4 Design's Levels of Abstraction

Mohamed Younis CMCS 411, Computer Architecture 5 Design Simulator q Device behavioral model is represented by procedure calls q Events that occur within the simulator are kept in a time-based queue q Events are stored as three-tuples (Module #, Pin #, New logic value) q Depending on the behavioral model of a module, the handling of an event usually trigger other events that will be inserted in the event queue Simulation continues until the event queue is empty or stopped externally by the designer Simulation continues until the event queue is empty or stopped externally by the designer

Mohamed Younis CMCS 411, Computer Architecture 6 Hardware Design Languages q A hardware design language provides primitive for describing both structural and behavioral models of the design q Hardware design languages are useful in è Documenting and modeling the design è Ensuring design portability q Every hardware design language is supported by a simulator that helps in: è validating the design è mitigating the risk of design faults è avoiding expensive prototyping for complicated hardware q VHDL and Verilog are the most famous and widely used hardware design language q Esim is a simplified and miniaturized version of VHDL to serve undergraduate education

Mohamed Younis CMCS 411, Computer Architecture 7 The Esim Design Languages q The esim language is purely digital in which signals can only take values of 0, 1, X for unknown, and Z for high impedance q Esim has primitives for both regular signals and memory, providing an efficient way to simulate microprocessor designs with registers and caches q Esim encourages hierarchical design by allowing the inclusion of modules in other modules q Esim's simulator is implemented as Tcl module, so it can be programmed to provide inputs to particular signals in the circuit q Design files are compiled (ecomp) generating a net list that can be validated through simulation (esim) ecomp test.e -o test.net q As most hardware design lang., all operations run in parallel Esim is developed by Ethan Miller and Jon Squire

Mohamed Younis CMCS 411, Computer Architecture 8 Hardware Descriptions in Esim Data types Ê Signal: è A single signal may have one of four different values: “0”, “1”, “Z” (undriven) or “X” (conflict/indeterminate). è Signals may be aggregated together, e.g. signal inputA[32]; Ë Memory è Used for register files or main memory è Values in memory remain until explicitly changed by memory statements è Memory can be initialized only using the simulator (not within esim program) Operations

Mohamed Younis CMCS 411, Computer Architecture 9 Hardware Descriptions in Esim q Expressions è Expressions may include signals and other expressions combined with operators: out <= (a & b) ^ (d | c) è The number of bits for operands for multi-input operation must match è Binary operators are performed bit-wise producing a result as wide as operands è Equality and inequality operations generate a one-bit results è A value “X” is treated as “do not care” and matches any value in conditional statement q Statements è All statement in esim operate in parallel è A statement takes the format : signal <= expression è Esim Statements can take two types of modifiers: H after: to specify a delay for the execution of the statement H on rising or falling: to specify edge triggered changes Example:a <= b on rising c after 10 ns

Mohamed Younis CMCS 411, Computer Architecture 10 Memory Operations q Declaration è Memory simulates variables whose values remain until explicitly changed è The reserved word memory should be used followed by the variable name similar to array declaration in C è Read and write to memory takes the form: read from [when ] write to [when ] q Example memory m[1024]; signal x[4], y[10], enb, clk; circuits m read x from y when enb; m write x to y[8:2]. #b00 when enb on rising clk; m write x[3:2] to y when enb; end circuits; Address in memory

Mohamed Younis CMCS 411, Computer Architecture 11 Esim’s Circuit Structure q Components è Basic hardware modules defined in esim are called components è Components may themselves include other components è Every component must be defined before it used. However, there is no limit to nesting levels è Parameters to the component definition do not specify input or output è Internal signals and definitions are not visible outside the component Example: // 8­bit latch clocked on the clk signal when enb1 and enb2 are both enabled define latch8 (q[8], d[8], enb1, enb2, clk) signal enabled; signal qInternal[8]; circuits qInternal <= d when (enb1 & enb2) else qInternal; q <= qInternal on rising clk; end circuits; end latch8; q Main Circuit è Use predefined components and do not define new ones è Include design input and output signals and system global memory

Mohamed Younis CMCS 411, Computer Architecture 12 Full Implementation of a 32-bit latch // 8-bit latch clocked on the clk signal when enb1 and enb2 are both enabled define latch8 (q[8], d[8], enb1, enb2, clk) ….. end latch8; // Set up a 16 bit latch as 2 8-bit latches define latch16 (q[16], d[16], clk) circuits low use latch8 (q[7:0], d[7:0], #b1, #b1, clk); // always enabled high use latch8 (q[15:8], d[15:8], #b1, #b1, clk); // always enabled end circuits; end latch16; // Top level circuits signal q[32]; signal d[32]; circuits low use latch16 (q[15:0], d[15:0], clk); high use latch16 (q[31:16], d[31:16], clk); end circuits; * example is courtesy of Ethan Miller The names preceding the use keyword allow the user to identify the different instances of latch8 in the simulator

Mohamed Younis CMCS 411, Computer Architecture 13 Defining a four way multiplexer with 8 bit signals // mux4_8 four eight bit inputs controlled by ctl to eight bit out define mux4_8(A[8], B[8], C[8], D[8], CTL[2], OUT[8]) circuits OUT<= with CTL select #b00: A; #b01: B; #b10: C; #b11: D; otherwise: A; // can't happen but need "otherwise" end select after 1ns; // fast gates end circuits; end mux4_8; Example * example is courtesy of Jon Squire

Mohamed Younis CMCS 411, Computer Architecture 14 Example Defining a general register component // “GREG” is general register set // memory is internal: // a1 address reads and outputs on out1 // a2 address reads and outputs on out2 // aw address writes input on wr & clk falling define GREG(a1[5], a2[5], aw[5], input[32], wr, clk, out1[32], out2[32]) memory mr[1024]; // 32 registers of 32 bits each circuits mr read out1 from a1.#b00000 when #b1; // always available mr read out2 from a2.#b00000 when #b1; mr write input to aw.#b00000 when wr on falling clk; end circuits; end GREG; * example is courtesy of Jon Squire The concatenation is equivalent to word alignment to get the right register

Mohamed Younis CMCS 411, Computer Architecture 15 Conclusion q Summary è Design phases (Design abstraction, design decomposition) è Hardware design languages (HDL) (Features, benefits, tools) è The “eSim ” a simple and miniaturized HDL (Structure, Reserved words, Declaration and statements, examples) q Next Lecture è Algorithms for multiplying unsigned numbers è Booth’s algorithm for signed number multiplication è Multiple hardware design for integer multiplier Reading assignment includes eSim paper and web pages