Full Adder Truth Table Conjugate Symmetry A B C CARRY SUM Mutually Complement 1 1 1 2 1 1 1 2 3 FC - on terms 3 1 1 1 4 1 1 7 6 5 4 FS - on terms 5 1 1 1 6 1 1 1 7 1 1 1 1 1 Conjugate Symmetry 1 In-Cheol Park

Full Adder Boolean equation Sum(Odd Parity) A×B×C CARRY A+B+C 2 In-Cheol Park

Which is better? Boolean Equation 1 : Boolean Equation 2 : CARRY evaluation is more urgent since CARRY is in the critical path S0 S1 S2 Sn C1 C2 Cn Cn ADDER ADDER ADDER ADDER C0 A0 B0 A1 B1 A2 B2 An Bn [ Ripple Carry Adder ] 3 In-Cheol Park

Alternating Complementary Form At Odd Stages At Even Stages A B C SUM CARRY A B C CARRY A B C SUM SUM SUM CARRY CARRY 4 In-Cheol Park

Dynamic Serial Adder A S B 5 In-Cheol Park A SUM B CARRY C R/S Q D CLOCK 5 In-Cheol Park

Looking at the FA Truth Table C CARRY SUM 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 In-Cheol Park

Transmission Gate Implementation A B C SUM A B A B B CARRY C A B 7 In-Cheol Park

CLA (Carry Lookahead Adder) P1 G1 P2 G2 P3 G3 P4 G4 C1 C2 C3 C4 An Bn Gn Pn 8 In-Cheol Park

Combining 4 Domino Carry Lookahead Blocks Manchester Carry Chain (4-bit) CK G1 P1 G2 P2 G3 P3 G4 P4 P1 P2 P3 P4 C0 C1 C2 C3 C4 MANCHESTER CARRY CHAIN C4 C0 C4 C0 G1 G2 G3 G4 CK C0 C1 C2 C3 C4 Limit @ 4 stages In the worst case, 6 Series Tr.s to the ground. 9 In-Cheol Park

Improving Worst Case Carry Prop. Time MANCHESTER CARRY CHAIN C0 C4 C0 C4 CK P1 P2 P3 P4 CK 10 In-Cheol Park

Manchester CC Adder Floorplan Dual CC Scheme One for Carry Prop. The other for off-loading the 1st CC from the SUM-block. GP SUM A4 MANCHESTER CARRY CHAIN MANCHESTER CARRY CHAIN BIT 4 S4 B4 GP SUM A3 MANCHESTER CARRY CHAIN MANCHESTER CARRY CHAIN BIT 3 S3 B3 GP SUM A2 MANCHESTER CARRY CHAIN MANCHESTER CARRY CHAIN BIT 2 S2 B2 SUM GENERATE SUM GENERATE A1 MANCHESTER CARRY CHAIN MANCHESTER CARRY CHAIN BIT 1 S1 B1 C0 11 In-Cheol Park

CSA (Carry Select Adder) A4 ~ A7 B4 ~ B7 C80 1 S41 ~ S71 1 S4 ~ S7 A4 ~ A7 B4 ~ B7 C81 C8 S40 ~ S70 S0 ~ S3 A0 ~ A3 B0 ~ B3 C0 C4 C80 C81 C8 C120 C121 A0 ~ A3 B0 ~ B3 C4 C0 S0 ~ S3 S0 ~ S3 12 In-Cheol Park

Minimization of Carry Propagation Path Delay Carry Select Scheme (prepare result for each case, Cin=1, Cin=0) Simplify the carry selection using the characteristic between Ci0 & Ci1 Take complement carries alternating the Even and Odd stages Adjust each block size with the consideration to the delay of carry select logic carry propagation delay of each block == carry propagation delay to the block adjust eg. for 32-bit path 4 4 5 6 6 7 13 In-Cheol Park

Carry Skip Adder Ripple Carry Adder와 CLA Adder의 Compromise b15 a13 b13 a3 b3 a1 b1 a14 b14 a12 b12 a2 b2 a0 b0 c16 c12 c8 c4 c0 P12, 15 P8, 11 P4, 7 14 In-Cheol Park

Comparison of Carry Select & Carry Skip A 32-bit Carry Select Adder A 32-bit Carry Skip Adder 15 In-Cheol Park

Conditional Sum Adder 16 In-Cheol Park MPX MPX MPX Triple 2-input MUX B2 A1 B1 A0 B0 S21 C31 S20 C30 S11 C21 S10 C20 S01 C11 S00 C10 MPX MPX MPX C0 S2 (C1=1) C3 (C1=1) S1 (C1=1) S2 (C1=0) C3 (C1=0) S1 (C1=0) S0 C1 Triple 2-input MUX S2 C3 S1 16 In-Cheol Park

Carry Lookahead Tree Adder Previous CLA implementation is not very adequate due to fan-in, fan-out problem & irregularity, despite the small(5) number of logic levels. Make it regular, using log2n - logic levels. a3 b3 a2 b2 g3 p3 g2 p2 G2,3 P2,3 G0,3 P0,3 a1 b1 a0 b0 g1 p1 g0 p0 G0,1 P0,1 ai bi gi pi Gj+1,k Pj+1,k Gi,k Pi,k Gi,j Pi,j [ 1st Part ] 17 In-Cheol Park

Carry Lookahead Tree Adder g2 p2 C1 C0 g0 p0 G0,1 P0,1 Cj+1 Ci Gi,j Pi,j Ci [ 2nd Part ] a3 b3 a2 b2 C0 a1 b1 a0 b0 S3 S2 S1 S0 C3 C2 C1 S3 ai bi gi pi Ci Pj+1,k Gj+1,k Cj+1,k Gi,j Pi,j Ci Gi,k Pi,k Ci [ Complete CLA Tree Adder ] 18 In-Cheol Park

Carry Save Adder Carry Save Adder is used wherever a large number of operands have to be added. F.A. ai bi ci 19 In-Cheol Park

Multiplier Add-and-Shift Algorithm multiplicand multiplier 1 + 1 1 + 1 multiplicand multiplier Multiplication procedure by Pencil-and-Paper Method Multiplication procedure by Add-and-Shift Algorithm 20 In-Cheol Park

The Serial-Parallel Multiplier B D D D D D D D D b2 D b1 D F.A F.A F.A F.A F.A F.A F.A b0 D D D D D D D D Output 21 In-Cheol Park

The Modified Booth Algorithm (cont’) Booth Encoder Table Booth Encoder b2k+1 1 b2k b2k-1 A multiplied by + x + 2x - 2x - x b2k-1 A = b2k b2k-1 b2k 2A b2k+1 negative = b2k+1 22 In-Cheol Park

Booth Multiplication Example Initial 0 Add -A 2-bit Shift Add 2A 01 11 -A 00 10 +2A 17 -9 Operation -153 + 23 In-Cheol Park

The Modified Booth Algorithm Let’s consider a number B = (bn-1, bn-2, ... , b1, b0) written in 2’s-complement. B may be rewritten as follows : Example In this equation, the terms in brackets is in the set {-2, -1, 0, 1, 2} n-bit multiplier generates exactly n/2 partial products 24 In-Cheol Park

Parallel Multiplier Multiplier has two basic operations The generation of partial products The summation of partial products Parallel multiplier avoids the overhead that is due to the separate controls of these two operations We speed up the multiplication The gain in speed is obtained at the expense of extra hardware Parallel multiplier can be implemented so as to support a high rate of pipelining 25 In-Cheol Park

The Braun Multiplier A straightforward implementation One bit of the new partial product ( ai . bj ) One bit of the previous partial product Carry in In the first four rows there is no horizontal carry propagation (using carry-save adder) a0 b0 a0b0 P0 a1 b1 a1b0 a0b1 P1 a2 b2 a2b0 a1b1 a0b2 P2 a3 b3 a3b0 a2b1 a1b2 a0b3 P3 a3b1 a2b2 a1b3 P4 a3b2 a2b3 P5 a3b3 P6 26 In-Cheol Park

The Braun Multiplier (cont’) F.A b0 b1 b2 b3 p0 p1 p2 p3 p4 p5 p6 p7 a0 a1 a2 a3 27 In-Cheol Park

Baugh-Wooley Multiplier Modified in order to allow multiplication of signed number Let’s consider 2 number A and B (2’s complement number) The product A.B is 28 In-Cheol Park

Baugh-Wooley Multiplier (cont’) F.A b0 b1 b2 b3 p0 p1 p2 p4 p5 p6 p7 p3 1 29 In-Cheol Park

Wallace Tree Multipliers Full adder vs Wallace tree Useful whenever a large number of operands are to add. Completion time in Braun or Baugh-Wooley multiplier Using Ripple Carry Adder: Proportional to the twice number of n of bits Using Wallace trees, Proportional to log2 (n) Full Adder 20 21 Wallace n 20 2n 21 30 In-Cheol Park

Recursive Decomposition of the Multiplication Partitioning two operands Four Terms (AH.BH, AH.BL, AL.BH, AL.BL) are computed using 4 p-bits multipliers The results are collected through Wallace tree 31 In-Cheol Park

Recursive Decomposition of the Multiplication BH BL AH AL AL X BL AH X BL AH X BH AL X BH AL X BL AL X BH AH X BH AH X BL 4 X W3 Adder AH AL BH BL Aligning the four partial products 32 In-Cheol Park

Booth’s Algorithm Array Multiplication Another approach to the design of a parallel multiplier for two’s complement operands The basic cell in rows i perform an add, subtract or transfer-only CASS (Controlled Add/Subtract/Shift) Cell cin Pin a H D cout 33 In-Cheol Park

Booth’s Algorithm Array Multiplication (cont’) CASS CTRL P6 x3 x2 x1 x0 P5 P4 P3 P2 P1 P0 a3 a2 a1 a0 H D Xi Xi-1 1 Shift Subtract Add d D H 34 In-Cheol Park

Booth Multiplier Booth Algorithm Parallel Multiplier No advantage over the previous multiplier Since the area (A) is of the order of n2, and T is linear in n Modified radix-4 Booth Algorithm Requires only n/2 rows of cells Reduce the delay (T) and the implementation cost( A) by a factor of two But actual delay and area gains are less than expected Because of recoding logic, partial product selector, large number of interconnections, longer delay per row 35 In-Cheol Park