1. Arithmetic Building Blocks
Datapath elements
Adder design
Static adder
Dynamic adder
Multiplier design
Array multipliers
Shifters, Parity circuits
ECE 261
Krish Chakrabarty

2. A Generic Digital ProcessorM E M O R Y
Input-Output C O N T R O L D A T A P A T H
ECE 261
Krish Chakrabarty

3. Building Blocks for Digital Architectures
Arithmetic unit -
Bit-sliced datapath (
adder
, multiplier,
shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
ECE 261
Krish Chakrabarty

4. Bit-Sliced Design Signals Data Control Data-in Multiplier Register
Metal 2
(control)
Signals
Data
Control C o n t r o l
Metal 1
(data) B i t 3 B i t 2
Data-in
Multiplier
Register
Data-out
Adder
Shifter B i t 1 B i t T i l e i d e n t i c a l p r o c e s s i n g e l e m e n t s
ECE 261
Krish Chakrabarty

5. Single-Bit Addition Half Adder Full Adder A B Cout S 1 A B C Cout S 11 A B C
Cout S 1
ECE 261
Krish Chakrabarty

6. Full-Adder A B F u l l C o u a d d e r C i n S u m t ECE 261
Krish Chakrabarty

7. The Binary Adder A B F u l l C i n C o u t a d d e r S u m
Sum = A  B  C
= ABCi + ABCi + ABCi + ABCi
Co = AB + BCi + ACi
ECE 261
Krish Chakrabarty

8. Sum and Carry as a functions of P, Ge f i n e 3 n e w v a r i a b l e w h i c h O N L Y d e p e n d o n A , B G e n e r a t e ( G ) = A B +B P r o p a g a t e ( P ) = A
ECE 261
Krish Chakrabarty

9. The Ripple-Carry AdderB S C o , i 1 2 3 ( = ) F W r s t c a e d e l a y l i n e a r w i t h t h e n u m b e r o f b i t s t = O ( N ) d
td = (N-1)tcarry + tsum G o a l : M a k e t h e f a s t e s t p o s s i b l e c a r r y p a t h c i r c u i t
ECE 261
Krish Chakrabarty

10. Complimentary Static CMOS Full Adder
Note:
1) S = ABCi + Co(A + B + Ci)
2) Placement of Ci
3) Two inverter stages for
each Co
O(N) delay
ECE 261
Krish Chakrabarty

11. Inversion Property Inverting all inputs results in inverted outputs
ECE 261
Krish Chakrabarty

12. Minimize Critical Path by Reducing Inverting StagesO d d C e l l A1 B1 A3 A0 A2 B3 B0 B2 C C C C C i , o , o , 1 o , 2 o , 3 F A ’ F A F A ’ F A S0 S1 S2 S3 E x p l o i t I n v e r s i o n P r o p e r t y
Need two different types of cells, FA’: no inverter in carry path
ECE 261
Krish Chakrabarty

13. A better structure: the Mirror Adder
ECE 261
Krish Chakrabarty

14. The Mirror Adder Symmetrical NMOS and PMOS chains
identical rising and falling transitions if the NMOS and PMOS devices are properly sized.
Maximum of two series transistors in the carry-generation circuitry.
Critical issue: minimization of the capacitance at Co.
Reduction of the diffusion capacitances important.
The capacitance at Co composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .
Transistors connected to Ci placed closest to output.
Only the transistors in carry stage have to be optimized for speed. All transistors in the sum stage can be minimal size.
ECE 261
Krish Chakrabarty

15. NP-CMOS Adder 17 transistors, ignoring extra inverters for inputs
and outputs
ECE 261
Krish Chakrabarty

16. Manchester Carry ChainV D D P C i , 1 G P 2 G 1 3  P 4
Co,4 G G 3 4 
Only nMOS transmission gates used. Why?
Delay of long series of pass gates: add buffers
ECE 261
Krish Chakrabarty

17. Carry-Bypass Adder I d e a : I f ( P a n d P 1 a n d P 2 a n d P 3 = 1G P G P G P G 1 1 2 2 3 3 C C i , C C C o , o , 1 o , 2 o , 3 F A F A F A F A P G P G P G P G 1 1 2 2 3 3 B P = P P P P o 1 2 3 C i , C o , C o , 1 C o , 2 F A F A F A F A C o , 3 I d e a : I f ( P a n d P 1 a n d P 2 a n d P 3 = 1 ) t h e n C = C , e l s e “ k i l l ” o r “ g e n e r a t e ” . o 3
ECE 261
Krish Chakrabarty

18. Manchester-Carry ImplementationC i , 1 G 2 3 B C o , 3
ECE 261
Krish Chakrabarty

19. Carry-Bypass Adder (cont.)u p C a r y P o g i n m B - 3 4 7 8 1 2 5 ,
Design N-bit adder using N/M equal length stages
e.g. N = 16, M = 4
What is the critical path?
tp = tsetup + Mtcarry + (N/M-1)tbypass + Mtcarry + tsum , i.e. O(N)
ECE 261
Krish Chakrabarty

20. Carry Ripple versus Carry Bypasst p r i p p l e a d d e r b y p a s s a d d e r 4 . . 8 N
ECE 261
Krish Chakrabarty

21. Carry-Select Adder
Generate carry out for both “0” and “1” incoming carries S e t u p P , G
4-bit block for bits
k, k+1, k+2, k+3
"
"
"
" C a r r y P r o p a g a t i o n
" 1
"
" 1
" C a r r y P r o p a g a t i o n C o , k - 1 M u l t i p l e x e r C o , k + 3 C a r r y V e c t o r S u m G e n e r a t i o n
ECE 261
Krish Chakrabarty

22. Carry Select Adder: Critical Path
ECE 261
Krish Chakrabarty

23. Carry-Select Adder: Linear Configuration
(1)
(1)
(5)
(5)
(5)
(5)
(5)
(6)
(7)
(8)
Are equal-sized blocks best?
ECE 261
Krish Chakrabarty

24. Linear Carry Select B i t - 3 B i t 4 - 7 B i t 8 - 1 1 B i t 1 2 - 1- 3 B i t 4 - 7 B i t 8 - 1 1 B i t 1 2 - 1 5 S e t u p
" C a r y 1 M l i x m G n o r y
" 1 C a M u l t i p e x S m G n o
" 1 S e t u p C a r y M l i x m G n o
"
"
" 1
" C C C C C i , o , 3 o , 7 o , 1 1 o , 1 5 S S S S - 3 4 - 7 8 - 1 1 1 2 - 1 5
ECE 261
Krish Chakrabarty

25. Square Root Carry Select
Bit 0-1
Bit 2-4
Bit 5-8
Bit 9-13 S e t u p
" C a r y 1 M l i x m G n o r y
" 1 C a M u l t i p e x S m G n o
" 1 S e t u p C a r y M l i x m G n o
(1)
"
"
(1)
" 1
"
(3)
(3)
(4)
(5)
(6)
(4)
(5)
(6) C C C C C i , o , 3 o , 7 o , 1 1 o , 1 5
i.e., O(N)
ECE 261
Krish Chakrabarty

26. Adder Delays - Comparison
ECE 261
Krish Chakrabarty

27. Carry Look-Ahead - Basic Idea
SN-1
Delay “independent” of the number of bits
ECE 261
Krish Chakrabarty

28. Carry-Lookahead Adders
High fanin for large N
Implement as CLA slices, or use 2nd level lookahead generator 4
16-bit CLA based on 4-bit
slices and ripple carry 4
CLA generator
Faster
implementation
ECE 261
Krish Chakrabarty

29. Look-Ahead: Topology VDD G3 G2 G1 G0 Ci,0 Co,3 P0 P1 P2 P3 Gnd ECE 261
Krish Chakrabarty