1. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Topics n Multipliers.

2. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Elementary school algorithm 0 1 1 0multiplicand x 1 0 0 1multiplier 0 1 1 0 + 0 0 0 0 0 0 1 1 0 + 0 0 0 0 0 0 0 1 1 0 + 0 1 1 0 0 1 1 0 1 1 0 partial product

3. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Word serial multiplier register +

4. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Combinational multiplier Uses n-1 adders, eliminates registers:

5. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Array multiplier n Array multiplier is an efficient layout of a combinational multiplier. n Array multipliers may be pipelined to decrease clock period at the expense of latency.

6. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Array multiplier organization 0 1 1 0 x 1 0 0 1 0 1 1 0 + 0 0 0 0 0 0 1 1 0 + 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 product skew array for rectangular layout multiplicand multiplier

7. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Unsigned array multiplier + x0y0x1y0x2y0 xn-1yn-1 0 x0y1 + x1y1 0 + x0y2 + x1y2 + 0 + P(2n-1) P(2n-2) P0

8. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Unsigned array multiplier, cont’d

9. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Array multiplier critical path

10. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Verilog for multiplier row module multrow(part,x,ym,yo,cin,s,cout); /* A row of one-bit multiplies */ input [2:0] part; input [3:0] x; input ym, yo; input [2:0] cin; output [2:0] s; output [2:0] cout; assign {cout[0],s[0]} = part[1] + (x[0] & ym) + cin[0]; assign {cout[1],s[1]} = part[2] + (x[1] & ym) + cin[1]; assign {cout[2],s[2]} = (x[3] & yo) + (x[2] & ym) + cin[2]; endmodule

11. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Verilog for last multiplier row module lastrow(part,cin,s,cout); /* Last row of adders with full carry chain. */ input [2:0] part; input [2:0] cin; output [2:0] s; output cout; wire [1:0] carry; assign {carry[0],s[0]} = part[0] + cin[0]; assign {carry[1],s[1]} = part[1] + cin[1] + carry[0]; assign {cout,s[2]} = part[2] + cin[2] + carry[1]; endmodule

12. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Verilog for multiplier module array_mult(x,y,p); input [3:0] x; input [3:0] y; output [7:0] p; wire [2:0] row0, row1, row2, row3, c0, c1, c2, c3; /* generate first row of products */ assign row0[2] = x[2] & y[0]; assign row0[1] = x[1] & y[0]; assign row0[0] = x[0] & y[0]; assign p[0] = row0[0]; assign c0 = 3’b000; multrow p0(row0,x,y[1],y[0],c0,row1,c1); assign p[1] = row1[0]; multrow p1(row1,x,y[2],y[1],c1,row2,c2); assign p[2] = row2[0]; multrow p2(row2,x,y[3],y[2],c2,row3,c3); assign p[3] = row3[0]; lastrow l({x[3] & y[3],row3[2:1]},c3,p[6:4],p[7]); endmodule

13. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Baugh-Wooley multiplier n Algorithm for two’s-complement multiplication. n Adjusts partial products to maximize regularity of multiplication array. n Moves partial products with negative signs to the last steps; also adds negation of partial products rather than subtracts.

14. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Booth multiplier n Encoding scheme to reduce number of stages in multiplication. n Performs two bits of multiplication at once—requires half the stages. n Each stage is slightly more complex than simple multiplier, but adder/subtracter is almost as small/fast as adder.

15. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Booth encoding n Two’s-complement form of multiplier: –y = -2 n y n + 2 n-1 y n-2 + 2 n-2 y n-2 +... n Rewrite using 2 a = 2 a+1 - 2 a : –y = -2 n (y n-1 -y n ) + 2 n-1 (y n-2 -y n-1 ) + 2 n-2 (y n-3 -y n-2 ) +... n Consider first two terms: by looking at three bits of y, we can determine whether to add/subtract x, 2x to partial product.

16. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Booth actions y i y i-1 y i-2 increment 0 0 00 0 0 1x 0 1 0x 0 1 12x 1 0 0-2x 1 0 1-x 1 1 0-x 1 1 10

17. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Booth example n x = 011001 (25 10 ), y = 101110 (-18 10 ). y 1 y 0 y -1 = 100, P 1 = P 0 - (10  011001) = 11111001110. y 3 y 2 y 1 = 111, P 2 = P 1  0 = 11111001110. n y 5 y 4 y 3 = 101, P 3 = P 2 - 0110010000 = 11000111110.

18. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Booth structure

19. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Wallace tree n Reduces depth of adder chain. n Built from carry-save adders: –three inputs a, b, c –produces two outputs y, z such that y + z = a + b + c n Carry-save equations: –y i = parity(a i,b i,c i ) –z i = majority(a i,b i,c i )

20. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Wallace tree structure

21. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Wallace tree operation n At each stage, i numbers are combined to form ceil(2i/3) sums. n Final adder completes the summation. n Wiring is more complex. n Can build a Booth-encoded Wallace tree multiplier.

22. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Serial-parallel multiplier n Used in serial-arithmetic operations. n Multiplicand can be held in place by register. n Multiplier is shfited into array.

23. FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Serial-parallel multiplier structure