2. Comparison of Various Multipliers for Performance Issues 24 March 2003. Depart. Of Electronics By: Manto Kwan High Speed & Low Power ASIC 97.575

3. Contents Introduction Twin-Piped Serial-Parallel Multiplier Array Multiplier Wallace Tree Multiplier Modified Booth Multiplier Combined Modified Booth- Wallace Tree Multiplier Conclusion 24 March 2003. Depart. Of Electronics, Page 2

4. Introduction Multiplier plays an very important role in today's digital circuits. The design of high speed, low power consumption, less area, and low irregularity in layout are very important. There are various types of multipliers:  Twin-Piped Serial-Parallel Multiplier,  Array Multiplier, Wallace Tree Multiplier,  Modified Booth Multiplier, and  Combined Modified Booth- Wallace Tree Multiplier. 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 3

5. Twin-Piped Serial- Parallel Multiplier Odd-indexed data bits and even- indexed data bits are processed in different clock phase and different circuits. Results in double throughput. The multiplier consists of 4 units. 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 4

6. Twin-Piped Serial- Parallel Multiplier The multiplicand is fed in parallel. The multiplier is fed in serial. The product is shifted out in series. Use where area and power consumption is restricted and speed is not important. 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 5

7. Array Multiplier Regular structure. Partial products are added and then shifted. 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 6

8. Wallace Tree Multiplier Partial Sum adders can be re- arranged in a tree-like fashion, reducing the critical path and the number of cells needed. Fig. (a) Only column 3 has to add 4 bits. All others are less complex. 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 7

9. Wallace Tree Multiplier Fig. (b) Half Adders (HA) in column 3 & 4. Fig.(c) Full Adders (FA) in column 3, 4, and 5; HA in column 2. Fig. (d) Finally, HA from column 1 to 6. 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 8

10. Wallace Tree Multiplier Wallace Tree multiplier implementation. Substantial saving on larger multiplier. 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 9

11. Modified Booth Multiplier Reduction on number of partial product by one half on average. Great savings on silicon area and increase in speed as the number of stage reduced by half.

12. Modified Booth Multiplier 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 11

13. Combined Modified Booth-Wallace Tree Multiplier Better area performance due to Modified Booth Algorithm and reduced delay due to Wallace Tree. However, building a regular structure becomes a challenge.

14. Comparison of 5 different multipliers Wallace tree multiplier and Combined Booth-Wallace tree multiplier have the least delay. Serial Parallel multiplier requires the least area and power when speed is not important.

15. Conclusion Each multiplier has its own advantage and disadvantage. Choice of a specific multiplier depends on application and constraint on area, power, delay. 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 14

16. Design Project Design an 8 bit Array Multiplier Using Logical Effort and Logical Balance. Compare the power consumption and delay. 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 15

17. Tentative Schedule Background Research  First half of April Designing  Third week of April onward Simulations  21-30 April 2003 Presentation  26-28 April 2003 Report  1-5 May 2003 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 16

18. The End The End 24 March 2003. Depart. Of Electronics24 March 2003. Depart. Of Electronics, Page 17