1. VLSI Digital System Design 1.Carry-Save, 2.Pass-Gate, 3.Carry-Lookahead, and 4.Manchester Adders

2. CS Adder Nomenclature ● Carry-SaveAdder (CSA) ● Carry-SelectAdder ● Carry-SkipAdder ● Conditional-SumAdder

3. Ripple-Carry Add Review ● Critical path: b1b1 a1a1 b0b0 a0a0 b3b3 a3a3 b2b2 a2a2 s2s2 s1s1 s0s0 s3s3 carry in carry out FA Critical path

4. Carry-Save Add ● Sum in redundant form b1b1 a1a1 c1c1 a0a0 b3b3 a3a3 b2b2 a2a2 s2s2 s1s1 s0s0 s3s3 FA b0b0 c2c2 c3c3 c1c1 c0c0 c2c2 c3c3 c0c0 Critical path

5. Carry-Save Add ● Reduce 3 binary numbers to 2 ● Also called 3:2 compressor – Examples of other compressors: 4:2, 7:1 ● Can create tree of CSAs to reduce arbitrary number of binary numbers – For example, to sum partial products ● Can compute final, nonredundant sum using carry-propagate adder ● Serial adder is special case of CSA

6. Pass-Gate Exclusive-Or Gate ● When a = 1, a ^ b = ~b, through b's inverter ● When a = 0, a ^ b = b, through pass gate ● Can also create Xnor gate – Swap a and ~a to b's inverter and pass gate ● 6 transistors. Circuit: a a ^ b b ~a

7. Pass-Gate Full-Adder Truth Table ● cabscoa^b 000000: b 001101: c 010101: c 011010: b 100100: b 101011: c 110011: c 111110: b ● carry out= (a ^ b) ? c : a = (a ^ b) ? c : b (if a ^ b, then a = b)

8. Pass-Gate Full-Adder Equations and Circuit ● s= (a ^ b) ^ c = (a ^ b) ? c : ~c ● carry out= (a ^ b) ? c : b(see errata) 1010 co 1010 s c b a

9. Pass-Gate Full-Adder Characteristics ● 24 transistors – 4 pass gates – 4 inverters – 2 Xor gates (which share their inverter portions) ● Delay to s = delay to co ● Both outputs, s and co, are uninverted

10. The Carry Recurrence ● C i = G i + P i C i-1 – C i A Carry out will leavestage i ● If – G i a carry is Generated instage i ● Or – C i-1 a Carry in enters fromstage i – 1 ● And – P i is Propagated bystage i

11. Carry-Lookahead Equations ● G i = A i * B i Generate ● P i = A i ^ B i Propagate ● C i = G i + P i C i-1 Carry = G i + T i C i-1 ● T i = A i + B i Transmit ● S i = C i-1 ^ A i ^ B i = C i-1 ^ P i – P i is a common subexpression to S i and C i

12. Transmit Can Replace Propagate ● T i can replace P i – With one exception ● P i = A i ^ B i Propagate ● T i = A i + B i Transmit ● C i = G i + T i C i-1 Carry ● S i = C i-1 ^ A i ^ B i ≠ C i-1 ^ T i – The exception to T i = P i

13. Carry-Lookahead Add ● G i = A i * B i ● P i = A i ^ B i ● S i = C i-1 ^ P i ● CG: Carry Generate Block b2b2 a2a2 b3b3 a3a3 b0b0 a0a0 b1b1 a1a1 s0s0 s1s1 s2s2 s3s3 ci c0c0 c1c1 c2c2 g0g0 g1g1 g2g2 g3g3 CG

14. Generalized Carry Recurrence ● C i = G i + P i C i-1 = G i + P i (G i-1 + P i-1 C i-2 ) = G i + P i G i-1 + P i P i-1 C i-2 = G i + P i G i-1 + P i P i-1 (G i-2 + P i-2 C i-3 ) = G i + P i G i-1 + P i P i-1 G i-2 + P i P i-1 P i-2 C i-3 ● C i = G i + n=1 Σ i ( m=n Π i P m )G n-1 + ( m=0 Π i P m )C 0

15. Unrolling the Carry Recurrence ● C i = G i + P i C i-1 ● C i = G i + n=i Σ 1 ( m=i Π n P m )G n-1 + ( m=i Π 0 P m )CI ● C 0 =G 0 +P 0 CI ● C 1 =G 1 +P 1 G 0 +P 1 P 0 CI ● C 2 =G 2 +P 2 G 1 +P 2 P 1 G 0 +P 2 P 1 P 0 CI ● C 3 = G 3 +P 3 G 2 +P 3 P 2 G 1 +P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 CI

16. Sum as an And Function of Transmit ● G= A * B ● T= A + B ● S= C ^ T* G' = C ^ (A + B)*(A* B)' = C ^ (A + B)*(A'+ B') = C ^ (AA' +AB' + BA' + BB') = C ^ (AB' + BA') = C ^ A ^ B – (See errata.)

17. Sum as a Nor Function of Transmit ● G= A * B ● T= A + B ● S= C ^ ( T'+ G)' = C ^ ((A + B)'+ (A* B ))' = C ^ ((A + B)* (A* B )') = C ^ ((A + B)* (A'+ B')) = C ^ (AA' +AB' + BA' + BB') = C ^ (AB' + BA') = C ^ A ^ B – (See errata.)

18. CarryEquation Common Subexpression Elimination ● C 3 = G 3 +P 3 G 2 +P 3 P 2 G 1 +P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 CI ● C 3 = G 3 +P 3 (G 2 +P 2 (G 1 +P 1 (G 0 +P 0 CI)))

19. Domino cMOS Carry Gate Circuit ● C 3 = G 3 + P 3 (G 2 + P 2 (G 1 + P 1 (G 0 + P 0 CI))) ● Worst-case delay path: – 6 nMOS in series p3p3 g3g3 p2p2 g2g2 p1p1 g1g1 p0p0 g0g0 ci clk c3c3

20. Dynamic Manchester Carry Chain Stage 1.Clk = 0, ~c n precharged by pMOS pull-up 2.Clk = 1, nMOS pull-down turned on 3.If g n = 1, ~c n discharges 4.If p n = 1, ~c n-1 may discharge ~c n gngn clk ~c n-1 pnpn ~c n

21. Dynamic Manchester Carry Chain Adder ● Carry is actually propagated ● 6 series nMOS transistors pull ~c 3 low g p ci co ~p ~c 2 p2p2 g2g2 ~p 2 g p ci co ~p ~c 3 p3p3 g3g3 ~p 3 g p ci co ~p ~ci p0p0 g0g0 ~p 0 g p ci co ~p ~c 1 p1p1 g1g1 ~p 1 c3c3 ci clk ~c 0

22. Dynamic Manchester Carry-Bypass Circuit ● Bypass the four stages if all p i are true g p ci co ~p ~c 2 p2p2 ~p 2 g p ci co ~p ~c 3 p3p3 ~p 3 g p ci co ~p ~ci p0p0 g0g0 ~p 0 g p ci co ~p ~c 1 p1p1 ~p 1 c3c3 ci clk ~c 0 p2p2 g2g2 p3p3 g3g3 p0p0 p1p1 g1g1

23. Conflict-Free Manchester Carry-Bypass Circuit ● Avoids conflicts at wired Or-node – Before final inverter – Improves speed. Note also inverter position 1010 g0g0 p2p2 ~g 2 ~g 3 p0p0 p1p1 g1g1 1010 210210 1010 ci c3c3 control