BDD-based Synthesis of Reversible Logic for Large Functions Robert Wille Rolf Drechsler DAC’09 Presenter: Meng-yen Li

Introduction Reversible Logic has become an intensely studied research area in recent years. Information loseless leads to low-power design. Basis for quantum computing. Further application in these domain optical computing DNA computing nanotechnologies

Introduction Current synthesis of reversible logic is very limited. In the previous proposed methods: Exact method’s limit when functions with  6 variables. Heuristic method at most 30 variables. Significant amount of run-time is needed to achieve these results.

Introduction The limitation is caused by underlying techniques. Those approaches rely on truth tables. Even if using more compact data structure like BDD, PPRM, RMS, same result is observed. Because previous methods apply same strategy: Selecting the reversible gates that is the identity of the chosen function.

Introduction In this work we introduce a synthesis method that can cope with significantly larger functions. Circuit obtained in linear time and with memory linear to the size of the BDD. Theoretical results for BDD can be transferred to reversible circuits. Circuit cost and run-time significantly improved. Function with large than 100 variables can be synthesized at very low run-time.

Preliminaries Reversible logic A logic function is reversible if each input assignment is mapped to unique output assignment.(Bijective, Permutation) So reversible circuit need same amount input and output.(lines in the circuit) A reversible circuit can be formed by cascading reversible gates.

Preliminaries A reversible gate has control line and target line. Target line is inverted if all control line are true.  XOR notation is put at the target line.  AND notation is put at the control lines.

Preliminaries The quantum cost(qc) of reversible circuit is the number of elementary quantum gates. Most used elementary quantum gate: NOT gate CNOT gate Controlled-V gate(square root of NOT) Controlled-V+ gate(invert of V, square root of NOT)

Preliminaries To realize non-reversible function in quantum circuit, non-reversible function need to be embedded into reversible function. The embedding adds constant inputs and garbage outputs. The garbage outputs is by definition don’t cares.(-)

Preliminaries Binary Decision Diagram(BDD) Boolean function can be represented by a BDD. A BDD is a directed acyclic graph G = (V,E) Shannon decomposition is carried out in each node v ∈ V. f =  x i f  xi + x i f xi (1 ≤ i ≤ n) f  xi (f xi ) is denoted by low(v) (high(v)) respectively. v is called the select variable size k is the number of non-terminal nodes.

Preliminaries BDD example Notation

Synthesis Approach General idea: A BDD is built for the function to be synthesized. Traversing in BDD and substituting each node with a cascade of reversible gates.

Synthesis Approach General case of substitution If low(f) and high(f) have no shared nodes in successors If low(f) or high(f) have shared nodes in successors The low(f) and high(f) are preserved

Synthesis Approach Special case of substitution(terminal node)

Synthesis Approach Examples

Synthesis Approach Examples

Algorithm The BDD is traversed by a depth-first search. For each node v  V, three checks are performed. Node v represents the identity of a primary input. The identity can be represent by the same input line. Node v contains at least one child is a terminal. Use substitution provided in Table 1. The successors of node v are still needed for other nodes. Use general case substitution in Table 1 to preserve successors. If above not holds, use figure 4. general substitution.

Theoretical Analysis Let f be the function with n inputs, and result BDD has k nodes. The Toffoli circuit consist of at most k+n circuit lines. 3k gates

Theoretical Analysis The result of BDD from previous study can be transferred to Toffoli circuit A BDD representing a single-output function has 2 n nodes in the worst case. Thus, each function can be realized in reversible logic with at most 3 ・ 2 n gates. At most 2 ・ 2 n CNOTs and 2 ・ 2 n Toffoli gates are needed according to the first row of Table 1.

Theoretical Analysis A BDD representing a symmetric function has n 2 nodes in the worst case. Thus, each symmetric function can be realized in reversible logic with at most 3 ・ n 2 gates. At most 2 ・ n 2 CNOTs and 2 ・ n 2 Toffoli gates are needed according to the first row of Table 1.

Theoretical Analysis A BDD representing specific symmetric functions, like AND, OR, or EXOR has a linear size. Thus, there exist a reversiblecircuit realizing these functions in linear size as well. A BDD representing an n-bit adder has linear size. Thus, there exist a reversible circuit realizing addition in linear size as well.

Expreimental Result RevLib for evaluating reversible synthesis. LGSynth for evaluating irreversible synthesis. AMD Athlon with 1 GB of memory. Timeout 500 CPU seconds. L. : number of lines. GC : gate counts QC : quantum cost QC EQ : QC of directly synthesis with elementary gates. ~ : the embedding is timeout. Time to build BDD is included in TIME.

Expreimental Result The resulting quantum cost are significantly lower in most of the cases. Quantum cost are more important than gate count since they consider gates with more control lines to be more costly. The total number of circuit lines that have been added by the BDD-BASED SYNTHESIS is moderate considering the obtained quantum cost reductions (in particular since all additional lines have constant inputs).

Conclusion This work introduced a synthesis approach which can cope with large functions. The BDD-based approach can synthesize circuits for functions with more than hundred variables in just a few CPU seconds. In most of the cases, reductions in the resulting quantum cost have been observed.

Future work The optimization of the resulting circuits. The number of additional lines should be reduced. Existing approaches provide a good starting point. Another idea is to adjust the cost function of exact BDD implementations with respect to quantum cost and to synthesize the circuits from the resulting BDDs.

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