BUILDING BLOCKS designed at IPHC in TOWER JAZZ CMOS Image Sensor 0.18 µm process Isabelle Valin on behalf of IPHC-PICSEL group

10/03/2014 INTRODUCTION The building blocks were initially designed in the AMS CMOS 0.35 µm process and have been translated in the TOWER JAZZ CMOS Image Sensor 0.18 µm process including:  Bandgap  Current reference  Bias-DAC  Reference voltage regulator  LVDS  JTAG controller Those blocks were implemented and tested in several prototype sensors. 2

10/03/2014 BANDGAP BANDGAP (W. Zhao)  Output voltage: V  High power supply rejection < -25 dB  Standard deviation [27 °C] 9.2 mV Process 2.5 mV Matching  Temperature coefficient [-45 to 140 °C] < 190 ppm/°C  Supply voltage range: 1.5 to 2 V  Power consumption ~130 µW [Typ, 27°C,1.8 V]  Reset  Dimension : x µm 2 3 Vout vs temperature for different process corners Vdd= 1.8 V PSR in process corners, Vdd= 1.8 V

10/03/2014 Current Reference (I.Valin) Reference current : 10 µA  Low dependency to temperature [-20 to 120 °C] and supply voltage [1.5 to 2 V]  Process variation compensated by Adjustment of the resistance value with 3 JTAG bits  Power consumption ~415 µW [Typ, 27°C,1.8 V]  Dimension: 94 x 110 µm 2 4 Current reference schematic IRef versus Vdd Iref versus temperature for different Vdd

10/03/2014 Bias-DAC (G. Bertolone, H. Pham, I.Valin) 8 bit current mode DAC  Programmable via the JTAG controller  Current steering segmented architecture:  2 bit DAC with binary weighted current cells  6 bit DAC with an array of 64 unit current cells  Monotonic DAC  Range: 0 – 25.5 µA, Step = 100 nA => Low power consumption  Dimension: 110 x 106 µm 2 5

10/03/2014 Reference Voltage Regulator (H.Pham) Generation of pixel clamping voltage, discriminator reference voltages 6 Architecture of the reference voltage regulator VREF0.6V DAC8-bit Vout Idac 0.9V-1.2V 0 – 0.8µAx255 R1=3K R2=6K 82° 59° Load Load Idac~51uA V V Line ±100mV0.3%

10/03/2014 LVDS LVDS receiver and driver (Z. Shi)  2 layout versions (Basic and Enclosed nmos)  LVDS disable option  Standard PAD compatible LVDS test (K. Jaaskelainen)  Receiver output connected to driver input  Test structure with differential transmision line (Z = 100 Ω ) of 30 cm length  Test input signal : XILINX IBERT Test Pattern Generator (PRBS-7) “DC-BALANCED DATA WITH LIMITED RUN-LENGTH“ 7 Test configuration 30 cm LVDS receiver schematic LVDS driver schematic

10/03/2014 LVDS LVDS test results  LVDS receiver + LVDS driver  Maximum data transfert Rate ~ 1 Gbps (or 500 MHz in case of clock signal)  Current consumption 7.6 static condition 10.1 Clock pattern at 1 Gbps 8 Eye amplitude vs Data bit rate Duty Cycle vs Data bit rateTotal jitter UI vs Data bit rate

10/03/ JTAG controller (C. Colledani, A. Himmi) JTAG protocol, IEEE 1149,1 Rev1999 standard Routed with 2 metal layers Dim. : 735 x112 µm 2 Basic hardware elements  Test Access Port (TAP),  TAP Controller,  Instruction Register (IR)  Device ID Register (Inputs: fuse or TIE1,TIE0), read only mode  Boudary Scan Register  2 specific data registers of 8 bits (read/write mode) History validated on MIMOSA Family + Mimosa28/Ultimate (STAR)  TCK Frequency ► 40MHz  Boundary Scan Clock  Timing analysis results ► slack (setup): 9 ns ► slack (hold): 0.12 ns  Test chip ► basic functions OK  TMS Setup/Hold Time ► ~2 ns  Boundary Scan Control Signal  TDI Setup/Hold Time ► ~2 ns  Boundary Scan Serial Data In  S.E.U protection  Standard Flip-Flop replaced with TMR Memory Cell (Triple Modular Redundancy)

10/03/2014 SUMMARY LVDS Driver/Receiver is full characterized. Other building blocks are validated by several prototype sensors test results but  Those blocks need to be implemented in a test chip for evaluating individually their performances.  To be optimized for power consumption.  To be redesigned without MIM Capacitors when keeping Metal5 & Metal6 for power supply redistribution layers. 10