1. DCD – Measurements and Plans
Ivan Perić
University of Heidelberg
Germany

2. Overview DCD measurements at full speed in Heidelberg.
Plans for the next chip version.

3. DCD – Measurements at 320 MHz (full speed)

4. DCD Characterization at 320MHz (Jochen’s test software)

5. DCD characterization with extended Sergey’s DAQ (320 MHz)
The DCD pedestal-current sources are used to generate a test picture – test of the synchronization.

6. DCD Pixel Signals and DCD Pedestals
The test current is turned on in the channels 0 and 1 – test of the synchronization.

7. Corrected with FPGA Pedestals
Pedestal correction in FPGA is used to compensate the test patterns.
Common mode noise is visible.

8. Shadow 30k Only one channel should see a high current per row.
There is a “shadow” of the signal in the row that follows – caused by a slow TIA response.
Row readout time is 100ns.

9. Shadow 60k
By increasing of TIA gain we increase the response time as well => shadow > 200ns.

10. Shadow 90k
By increasing TIA gain we increase the settling time as well => shadow > 300ns.

11. Shadow 30k – IL5
The speed of the amplifier can be increased by decreasing IL bias setting.

12. Noise IL5
Noise 0.7 LSBs (60 nA).

13. Pedestals IL5
Pedestal and noise corrected.

14. Power consumption and voltages
Name
Voltage at the chip (referred to chip gnd)
Voltage at the power supply
Current consumption at the power supply
Vddd
1.84 (1.74)
2.00
268mA
Gndd
0.10 (0.00)
0.00
Vdda
1.89 (1.78)
2.05
286mA
RefIn
1.16 (1.05)
1.25
60mA
AmpLow
0.47 (0.36)
0.40
182mA
Gnda
0.11 (0.00)
Power = Vddd x Ivdd + RefIn x IRefIn + Vdda x Ivdda + (Vdda-AmpLow) x IAmpLow
Power = 1.74 x 268mA x 60mA x 286mA x 182mA = = 1.297mW

15. Power consumption and voltages
286
=468
1.8V
Vdda 60
1.05V
182
RefIn
0.36V
AmpLow 0V
Gnda
286+60=346
268
1.8V
Vddd 0V
Gndd

16. DCD – Plans for the next Chip

17. Comparator
In certain number of channels (~1%) the ADC characteristics show missing codes when they are operated at standard bias settings.
This is most probably cased by an inaccurate comparison of the signals.
The effect can be removed by increasing of RefIn and decreasing of VNMOS voltage (increasing of the DAC value).
Simulation
RefIn C
VNMOS

18. The bridge protects from antenna effect.
Comparator
The effects resemble the ones we have already seen in DCD1/2 (the old ILC prototypes).
We have repaired this by adding additional metal-metal capacitors.
The broken comparators have most probably a problem in their metal-metal capacitors.
Possible antenna-effect combined with many single contacts in series.
Now:
Should be:
Ctr
Cmim
The bridge protects from antenna effect.

19. Proposed Changes in new DCDB
Make a temperature-stabile reference circuits with the possibility to use old scheme optionally.
Add regulated cascode in TIA with the possibility to use old scheme optionally.
Decrease TIA gain settings: 1, 2, 3 => 0.5, 1, 2.
Make global register SEU tolerant (?).
Increase digital-output current, or add a boost setting.
Add a power regulators for AmpLowAmp and AmpLowADC.
Add a L/R bit in every channel and an additional offset correction source controlled by this bit.
Check if the input protection can cope with gated mode operation.
Add the possibility to exclude unused channels from common mode network. IP IL
Not a f(T)
Use old
Out
Vcasc
ISF In
~1/KT
~KT

20. Summary
DCD works stabile at 320 MHz. (The measurements have been performed with 4.1. hybrid using DCDRO.)
Small number of channels show missing digital codes when operated at the standard settings. The channels can be recovered by changing two bias voltages that affect the comparators.
The effect is most probably caused by the unconnected metal – metal capacitors in the comparators. This layout problem will be repaired in the next chip.
Several small changes have been proposed for the next submission.