1 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 17: Wed 10/21/2011 (Midterm Overview) Instructor: Dr. Phillip Jones Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA

2 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) MP3: Due 11/4 Weekly Project Updates due: Friday’s (midnight) Announcements/Reminders

3 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) Project Grading Breakdown 50% Final Project Demo 30% Final Project Report –20% of your project report grade will come from your 5-6 project updates. Friday’s midnight 20% Final Project Presentation

4 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) FPL FPT FCCM FPGA DAC ICCAD Reconfig RTSS RTAS ISCA Projects Ideas: Relevant conferences Micro Super Computing HPCA IPDPS

5 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) Teams Formed and Topic: Mon 10/10 –Project idea in Power Point 3-5 slides Motivation (why is this interesting, useful) What will be the end result High-level picture of final product –Project team list: Name, Responsibility High-level Plan/Proposal: Fri 10/14 –Power Point 5-10 slides (presentation to class Wed 10/19) System block diagrams High-level algorithms (if any) Concerns –Implementation –Conceptual Related research papers (if any) Projects: Target Timeline

6 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) Work on projects: 10/ /9 –Weekly update reports More information on updates will be given Presentations: Finals week –Present / Demo what is done at this point –15-20 minutes (depends on number of projects) Final write up and Software/Hardware turned in: Day of final (TBD) Projects: Target Timeline

7 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) Initial Project Proposal Slides (5-10 slides) Project team list: Name, Responsibility (who is project leader) –Team size: 3-4 (5 case-by-case) Project idea Motivation (why is this interesting, useful) What will be the end result High-level picture of final product High-level Plan –Break project into mile stones Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip. –System block diagrams –High-level algorithms (if any) –Concerns Implementation Conceptual Research papers related to you project idea

8 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) Weekly Project Updates The current state of your project write up –Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section The current state of your Final Presentation –Your Initial Project proposal presentation (Due Wed 10/19). Should make for a starting point for you Final presentation What things are work & not working What roadblocks are you running into

9 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) Common Questions

10 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) Common Questions

11 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) How many 6-input LUTs needed MidTerm (Q1.a)

12 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) How many 6-input LUTs needed Ans: 2 MidTerm (Q1.a)

13 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) How many 6-input LUTs needed Ans: 2 MidTerm (Q1.a)

14 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) How many 6-input LUTs needed Ans: 2 MidTerm (Q1.a)

15 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) i) What would be 2 disadvantages of using 3-LUTs instead of 6-LUTs in part a)? (2pts) ii) If you had to manufacture an FPGA device to support applications that used MANY 2- to-1 multiplexers, would you make the FPGA primitives 6-LUTs or 3-LUTs. What would be 2 advantages of using your choice compared to the alternative? (2 pts) More LUTs needed iii) In general discuss some of the trade-offs between having an FPGA made up of 4- LUTs vs 20-LUTs (3 pts) MidTerm (Q1.b)

16 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) i) What would be 2 disadvantages of using 3-LUTs instead of 6-LUTs in part a)? (2pts) –More LUTs needed –More Routing resources needed –More area of the chip will be used –Large latencies (i.e. slower 4-1 mux) ii) If you had to manufacture an FPGA device to support applications that used MANY 2- to-1 multiplexers, would you make the FPGA primitives 6-LUTs or 3-LUTs. What would be 2 advantages of using your choice compared to the alternative? (2 pts) More LUTs needed iii) In general discuss some of the trade-offs between having an FPGA made up of 4- LUTs vs 20-LUTs (3 pts) MidTerm (Q1.b)

17 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) i) What would be 2 disadvantages of using 3-LUTs instead of 6-LUTs in part a)? (2pts) –More LUTs needed –More Routing resources needed –More area of the chip will be used –Large latencies (i.e. slower 4-1 mux) ii) If you had to manufacture an FPGA device to support applications that used MANY 2- to-1 multiplexers, would you make the FPGA primitives 6-LUTs or 3-LUTs. What would be 2 advantages of using your choice compared to the alternative? (2 pts) More LUTs needed –3-LUT –2-1 mux can map directly –With 6-LUT, 3 unused pins, thus unused logic –With 6-LUT, slower 2-1 mux because of extra logic to propagate through –6-LUT will take up more chip area (6-LUTs are larger than 3-LUTs) iii) In general discuss some of the trade-offs between having an FPGA made up of 4- LUTs vs 20-LUTs (3 pts) MidTerm (Q1.b)

18 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) i) What would be 2 disadvantages of using 3-LUTs instead of 6-LUTs in part a)? (2pts) ii) If you had to manufacture an FPGA device to support applications that used MANY 2- to-1 multiplexers, would you make the FPGA primitives 6-LUTs or 3-LUTs. What would be 2 advantages of using your choice compared to the alternative? (2 pts) More LUTs needed iii)In general discuss some of the trade-offs between having an FPGA made up of 4- LUTs vs 20-LUTs (3 pts) MidTerm (Q1.b)

19 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) i) What would be 2 disadvantages of using 3-LUTs instead of 6-LUTs in part a)? (2pts) ii) If you had to manufacture an FPGA device to support applications that used MANY 2- to-1 multiplexers, would you make the FPGA primitives 6-LUTs or 3-LUTs. What would be 2 advantages of using your choice compared to the alternative? (2 pts) More LUTs needed iii)In general discuss some of the trade-offs between having an FPGA made up of 4- LUTs vs 20-LUTs (3 pts) –For simple circuits (bit-level manipulation) smaller 4-LUT better Less wasted resources Faster –For complex circuits (an ALU) larger LUT 20-LUT may be better Less LUTs to connect together (less routing needed) (less overall area used as compared to smaller LUTS Less delay due to extra wires Easier for tools to place and route MidTerm (Q1.b)

20 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) ) Discuss the reasons why an application implemented using an FPGA will typically be lower performing than an application implemented as an application specific integrated circuit (ASIC) (5 pts) ii) What are some of the reasons why a person (or company) may choose to use an FPGA instead of an ASIC to implement an application? (4pts) MidTerm (Q1.c)

21 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) ) Discuss the reasons why an application implemented using an FPGA will typically be lower performing than an application implemented as an application specific integrated circuit (ASIC) (5 pts) – Over head due to routing resource to allow general purpose routeing, while ASIC only has exactly routing wire needed for the design (FPGA my be made up of 90% routing resources –ASIC logic is optimzed at the gate level, while FPGA use a general purpose LUT for all logic. LUT may have left over logic not used Many LUT may need to be wired together (slower overall logic) ii) What are some of the reasons why a person (or company) may choose to use an FPGA instead of an ASIC to implement an application? (4pts) MidTerm (Q1.c)

22 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) ) Discuss the reasons why an application implemented using an FPGA will typically be lower performing than an application implemented as an application specific integrated circuit (ASIC) (5 pts) – Over head due to routing resource to allow general purpose routeing, while ASIC only has exactly routing wire needed for the design (FPGA my be made up of 90% routing resources –ASIC logic is optimized at the gate level, while FPGA use a general purpose LUT for all logic. LUT may have left over logic not used Many LUT may need to be wired together (slower overall logic) ii) What are some of the reasons why a person (or company) may choose to use an FPGA instead of an ASIC to implement an application? (4pts) – ASICs cost a lot, and only make sense to use if you are make MANY devices –FPGAs can be reconfigured after deployment Can apply HW upgrades in the field Can apply HW fixes in the field –Development time less (FPGA: 1 day – months, ASIC: months - year) –Time share hardware: Can place multiple functionary on one chip –Intial ASIC testing (Modelsim slow), And early SW testing MidTerm (Q1.c)

23 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) LUT configurability: How many different ways can a 6-LUT be configured? Explain how you arrived at your number. (Note it my help to use a figure for your explanation) (5pts) MidTerm (Q1.d)

24 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) MidTerm (Q2.a)

25 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) MidTerm (Q2.b)

26 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) process(clk) if(clk’event and clk =1) then C <= B; end if; end process process(X, B, C, D, E) if(X = ‘0’) then A <= B or C; else case D is when ‘00’ => A<= E and B; when ‘01’ => A<= E xor B; when ‘10’ => A<= ‘1’; when ‘11’ => A<= ‘0’; end case; end if; end process MidTerm (Q2.c)

27 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) process(sel, a, b) begin if(sel = ‘1’ and b=’1’) then z <= ‘1’; elsif(sel = ‘0’ and b = ‘1’ and a = ‘0’) then z <= c; end if; end process; process(sel_1) begin z <= ‘1’; if(sel_1 = ‘0’) then z <= ‘1’; else z <= ‘0’; end if; end process; MidTerm (Q2.d)

28 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) Why would a company use an array of FPGAs to implement a large circuit like a commercial microprocessor? MidTerm (Q3.a)

29 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) MidTerm (Q3.a)

30 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) Why is Reconfiguration management important? MidTerm (Q3.b)

31 - ECpE 583 (Reconfigurable Computing): Midterm Overview Iowa State University (Ames) a) Write a line of VHDL that converts a lower case ASCII letter to an upper case letter (Note: you do not need to use exact numbers) (5 pts) b) What did the “TX_busy_n” signal of the UART interface indicate? Explain how you made use of this signal in your MP 1 (5 pts) c) What did the “RX_full” signal of the UART interface indicate? Explain how you made use of this signal in your MP 1 (5 pts) MidTerm (Q4)