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1 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 12: Wed 10/6/2010 (Compute.

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Presentation on theme: "1 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 12: Wed 10/6/2010 (Compute."— Presentation transcript:

1 1 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 12: Wed 10/6/2010 (Compute Models) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ee.iastate.edu/cpre583/

2 2 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) HW2: Due Wed 10/6 (today) –Problem 2 will have a separate deadline (to be announced) Midterm: –Take home portion (40%) given Friday 10/15, due Tue 10/20 (midnight) –In class portion (60%) Wed 10/20 Distance students will have in class portion given via a timed WebCT (2 hour) session (take on Wed, Thur or Friday). Start thinking of class projects and forming teams –Submit teams and project ideas: Mon 10/11 midnight –Project proposal presentations: Fri 10/22 MP3: PowerPC Coprocessor offload overview Announcements/Reminders

3 3 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Initial Project Proposal Slides (5-10 slides) Project team list: Name, Responsibility (who is project leader) –Team size: 3-4 (5 case-by-case) Project idea Motivation (why is this interesting, useful) What will be the end result High-level picture of final product High-level Plan –Break project into mile stones Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip. –System block diagrams –High-level algorithms (if any) –Concerns Implementation Conceptual Research papers related to you project idea

4 4 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) FPL FPT FCCM FPGA DAC ICCAD Reconfig RTSS RTAS ISCA Projects Ideas: Relevant conferences Micro Super Computing HPCA IPDPS

5 5 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Initial Project Proposal Slides (5-10 slides) Project team list: Name, Responsibility (who is project leader) Project idea Motivation (why is this interesting, useful) What will be the end result High-level picture of final product High-level Plan –Break project into mile stones Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip. –System block diagrams –High-level algorithms (if any) –Concerns Implementation Conceptual Research papers related to you project idea

6 6 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Weekly Project Updates The current state of your project write up –Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section The current state of your Final Presentation –Your Initial Project proposal presentation (Due Fri 10/22). Should make for a starting point for you Final presentation What things are work & not working What roadblocks are you running into

7 7 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Teams Formed and Idea: Mon 10/11 –Project idea in Power Point 3-5 slides Motivation (why is this interesting, useful) What will be the end result High-level picture of final product –Project team list: Name, Responsibility High-level Plan/Proposal: Fri 10/22 –Power Point 5-10 slides System block diagrams High-level algorithms (if any) Concerns –Implementation –Conceptual Related research papers (if any) Projects: Target Timeline

8 8 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Work on projects: 10/22 - 12/8 –Weekly update reports More information on updates will be given Presentations: Last Wed/Fri of class –Present / Demo what is done at this point –15-20 minutes (depends on number of projects) Final write up and Software/Hardware turned in: Day of final (TBD) Projects: Target Timeline

9 9 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Project Grading Breakdown 50% Final Project Demo 30% Final Project Report –30% of your project report grade will come from your 5-6 project updates. Friday’s midnight 20% Final Project Presentation

10 10 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Common Questions

11 11 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Common Questions

12 12 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Common Questions

13 13 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Common Questions

14 14 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Compute Models Overview

15 15 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Introduction to Compute Models What you should learn

16 16 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Design patterns (previous lecture) –Why are they useful? –Examples Compute models (Abstraction) –Why are they useful? –Examples System Architectures (Implementation) –Why are they useful? –Examples Outline

17 17 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Design patterns (previous lecture) –Why are they useful? –Examples Compute models (Abstraction) –Why are they useful? –Examples System Architectures (Implementation) –Why are they useful? –Examples Outline

18 18 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) References Reconfigurable Computing (2008) [1] –Chapter 5: Compute Models and System Architectures Scott Hauck, Andre DeHon Design Patterns for Reconfigurable Computing [2] –Andre DeHon (FCCM 2004) Type Architectures, Shared Memory, and the Corollary of Modest Potential [3] –Lawrence Snyder: Annual Review of Computer Science (1986)

19 19 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Problem -> Compute Model + Architecture -> Application Questions to answer –How to think about composing the application? –How will the compute model lead to a naturally efficient architecture? –How does the compute model support composition? –How to conceptualize parallelism? –How to tradeoff area and time? –How to reason about correctness? –How to adapt to technology trends (e.g. larger/faster chips)? –How does compute model provide determinacy? –How to avoid deadlocks? –What can be computed? –How to optimize a design, or validate application properties? Building Applications

20 20 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Compute Models [1]: High-level models of the flow of computation. Useful for: –Capturing parallelism –Reasoning about correctness –Decomposition –Guide designs by providing constraints on what is allowed during a computation Communication links How synchronization is performed How data is transferred Compute Models

21 21 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Data Flow: –Single-rate Synchronous Data Flow –Synchronous Data Flow –Dynamic Streaming Dataflow –Dynamic Streaming Dataflow with Peeks –Steaming Data Flow with Allocation Sequential Control: –Finite Automata (i.e. Finite State Machine) –Sequential Controller with Allocation –Data Centric –Data Parallel Two High-level Families

22 22 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Graph of operators that data (tokens) flows through Composition of functions Data Flow XX +

23 23 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Graph of operators that data (tokens) flows through Composition of functions Data Flow XX +

24 24 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Graph of operators that data (tokens) flows through Composition of functions Data Flow XX +

25 25 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Graph of operators that data (tokens) flows through Composition of functions Data Flow XX +

26 26 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Graph of operators that data (tokens) flows through Composition of functions Data Flow XX +

27 27 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Graph of operators that data (tokens) flows through Composition of functions Data Flow XX +

28 28 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Graph of operators that data (tokens) flows through Composition of functions Data Flow XX +

29 29 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Graph of operators that data (tokens) flows through Composition of functions Captures: –Parallelism –Dependences –Communication Data Flow XX +

30 30 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) One token rate for the entire graph –For example all operation take one token on a given link before producing an output token –Same power as a Finite State Machine Single-rate Synchronous Data Flow - 1 1 update 1 F 1 1 1 copy 1 1 1 1 1

31 31 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Each link can have a different constant token input and output rate Same power as signal rate version but for some applications easier to describe Automated ways to detect/determine: –Dead lock –Buffer sizes Synchronous Data Flow - 1 1 update 1 F 1 10 copy 1 1 1 10 1

32 32 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Token rates dependent on data Just need to add two structures –Switch Select Dynamic Steaming Data Flow Switch Select S S in0in1 out in out0out1

33 33 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Token rates dependent on data Just need to add two structures -Switch, Select More –Powerful –Difficult to detect Deadlocks Still Deterministic Dynamic Steaming Data Flow Switch S Select x x y y F0F1 1 x x y y

34 34 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Allow operator to fire before all inputs have arrived –Example were this is useful is the merge operation Now execution can be nondeterministic –Answer depends on input arrival times Dynamic Steaming Data Flow with Peeks Merge

35 35 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Allow operator to fire before all inputs have arrived –Example were this is useful is the merge operation Now execution can be nondeterministic –Answer depends on input arrival times Dynamic Steaming Data Flow with Peeks Merge A

36 36 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Allow operator to fire before all inputs have arrived –Example were this is useful is the merge operation Now execution can be nondeterministic –Answer depends on input arrival times Dynamic Steaming Data Flow with Peeks Merge B A

37 37 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Allow operator to fire before all inputs have arrived –Example were this is useful is the merge operation Now execution can be nondeterministic –Answer depends on input arrival times Dynamic Steaming Data Flow with Peeks Merge B A

38 38 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Removes the need for static links and operators. That is the Data Flow graph can change over time More Power: Turing Complete More difficult to analysis Could be useful for some applications –Telecom applications. For example if a channel carries voice verses data the resources needed may vary greatly Can take advantage of platforms that allow runtime reconfiguration Steaming Data Flow with Allocation

39 39 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Sequence of sub routines –Programming languages (C, Java) –Hardware control logic (Finite State Machines) Transform global data state Sequential Control

40 40 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Finite state Can verify state reachablilty in polynomial time Finite Automata (i.e. Finite State Machine) S1 S2 S3

41 41 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Adds ability to allocate memory. Equivalent to adding new states Model becomes Turing Complete Sequential Controller with Allocation S1 S2 S3

42 42 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Adds ability to allocate memory. Equivalent to adding new states Model becomes Turing Complete Sequential Controller with Allocation S1 S2 S3 S4 SN

43 43 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Multiple instances of a operation type acting on separate pieces of data. For example: Single Instruction Multiple Data (SIMD) –Identical match test on all items in a database –Inverting the color of all pixels in an image Data Parallel

44 44 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Similar to Data flow, but state contained in the objects of the graph are the focus, not the tokens flowing through the graph –Network flow example Data Centric Source1 Dest1 Dest2 Switch Source2 Source3 Flow rate Buffer overflow

45 45 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Multi-threaded: a compute model made up a multiple sequential controllers that have communications channels between them Very general, but often too much power and flexibility. No guidance for: –Ensuring determinism –Dividing application into threads –Avoiding deadlock –Synchronizing threads The models discussed can be defined in terms of a Multi-threaded compute model Multi-threaded

46 46 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Multi-threaded (Illustration)

47 47 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Thread: is an operator that performs transforms on data as it flows through the graph Thread synchronization: Tokens sent between operators Streaming Data Flow as Multithreaded

48 48 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Thread: is a data item Thread synchronization: data updated with each sequential instruction Data Parallel as Multithreaded

49 49 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Use when a stricter compute model does not give enough expressiveness. Define restrictions to limit the amount of expressive power that can be used –Define synchronization policy –How to reason about deadlocking Caution with Multithreaded Model

50 50 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) “A Framework for Comparing Models of computation” [1998] –E. Lee, A. Sangiovanni-Vincentelli –Transactions on Computer-Aided Design of Integrated Circuits and Systems “Concurrent Models of Computation for Embedded Software”[2005] –E. Lee, S. Neuendorffer –IEEE Proceedings – Computers and Digital Techniques Other Models

51 51 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Next Lecture System Architectures

52 52 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) MP3 FPGA PC Display.c Ethernet (UDP/IP) Power PC User Defined Instruction Monitor VGA

53 53 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) MP3 FPGA PC Display.c Ethernet (UDP/IP) Power PC User Defined Instruction Monitor VGA

54 54 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) MP3 FPGA PC Display.c Ethernet (UDP/IP) Power PC User Defined Instruction Monitor VGA

55 55 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) MP3 Notes MUCH less VHDL coding than MP2 But you will be writing most of the VHDL from scratch The focus will be more on learning to read a specification (Power PC coprocessor interface protocol), and designing hardware that follows that protocol. You will be dealing with some pointer intensive C-code. It’s a small amount of C code, but somewhat challenging to get the pointer math right.

56 56 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Questions/Comments/Concerns Write down –Main point of lecture –One thing that’s still not quite clear –If everything is clear, then give an example of how to apply something from lecture OR

57 57 - CPRE 583 (Reconfigurable Computing): Compute Models Iowa State University (Ames) Lecture Notes kk


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