1. CPRE 583 Reconfigurable Computing
Lecture 8: 9/17/2010 (VHDL to FPGA: A Tool Flow Overview )
Instructor: Dr. Phillip Jones
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA

2. Announcements/Reminders
HW2: will be released by 5pm Friday
MP2: Make sure to get starting ASAP!
Make sure to read the README file in the MP2 distribution
Contains info on how to fix a Gigabit core licensing issue ISE has
Mini literary survey
PowerPoint tree due Today.
Final 5-10 page write up on your tree due: Fri 9/24 midnight.
Should tell the story of your literary tree
Week extension for those that decide today they may what to do a survey on today’s topic

3. Literary Survey
Start with searching for papers from on IEEE Xplorer:
Advanced Search (Full Text & Meta data)
Find popular cross references for each area
For each area try to identify 1 good survey papers
For each area
Identify 2-3 core Problems/issues
For each problem identify 2-3 Approaches for addressing
For each approach identify 1-2 papers that Implement the approach.

4. Literary Survey: Example Structure
Network Intrusion
Detection P1 P2 P3 A1 A2 A3 A1 A2 A1 A2 I1 I1 I2 I1 I1 I1 I1 I2 I1
5-10 page write up on your survey tree

5. Fall 2010 Student Example Network Intrusion Detection Systems
detection accuracy
signatures
The Study on Network Intrusion Detection System of Snort
heuristics
An FPGA-Based Network Intrusion Detection Architecture
adaptability to new threats
neural networks
Network Intrusion Detection Method Based on Radial Basic Function Neural Network
principal component analysis
An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System
support vector machine
Network Intrusion Detection Based on Support Vector Machine
Network Intrusion Detection Method Based on Agent and SVM

6. Common Questions

7. Common Questions

8. Common Questions

9. Common Questions

10. Overview Introduction to mapping VHDL to FPGA hardware
What you should learn
What are the major steps?
What is the basic purpose of each step?

11. Major Steps Input Hardware Description Langue (HDL) Synthesis Map
Place & Route
Hardware configuration file generation

12. Graphical flow
Implement
Simulate
Synthesize
Map
Place
Route
Download

13. Major Steps (Text: Chapters 13-20)
Z <= (A and B) or C;
Input VHDL description Z A B
Transform VHDL into primitive
gates (synthesis) C
LUT A B C Z
Transform primitive to technology
dependent primitives (MAP)
Associate primitive with specific
Instances, and connect using
Routing resources (PAR)
LUT A B C Z
Encode placement and routing
description into a configuration file
for programming a specific FPGA type
000 A B C
101 Z

14. High Level Design Description
VHDL
Verilog
C type languages (e.g. handle C)
Typically auto transformed into VHDL or Verilog
Schematic capture (I believe ISE has this option)
Gate level (connecting structural components)
Statemachine bubble diagrams
High level graphical
Simulink/System Generator (Xilninx)
Simulink/DSP Builder (Altera)
System on chip embedded system design
Xilinx EDK:
Altera SoPC:

15. Synthesis Application of Boolean logic theory
Technology independent representation
EDIF (Electronic Design Interchange Format)
Technology independent optimization
Combinational optimization
2-level
Multi-level
Sequential optimization
FSM state reduction
retiming

16. EDIF representation
Gives a standard means to target a design to different vendors
Example EDIF file

17. Combinational Optimization
This is a major area of active research!
ABC from Berkeley provides and open source tool
This is a great starting place if you think you maybe interested in pursuing research in VLSI Computer Automation Design Tool development.
I plan to try to incorporate this tool in an homework assignment later in the semester.

18. MAP (Technology Mapping: Chapter 13)
Translate device independent net list to device specific resources (for FPGAs a common device specific resource is a LUT)
Structural:
Maintains structure
Functional:
Will modify structure for optimization A Z
LUT A Z B B C C

19. PAR (Place and Route: Chapters 14-17)
Place: Text Chapters 14 and 16 fundamentals
Route: Text Chapter 17 fundamentals
Tools and Challenge
VPR:
Pathfinder: (looking for some open source)
Open challenge (make some money?)

20. Place (Chapter 17)
Bind each mapped resources to a physical device location
General Purpose
Placing resources without knowledge of high level structure. Guided by local connection between resources
Structured Guided
Makes assumptions about the structure of the circuit to guide placement. If circuit does not follow assumption will like give poor placement
User Guided Layout
User provides guidance to the algorithm to help with placement
Some way to provide this information
VHDL directives (e.g. relative location constraints RLOC)
GUI-based (e.g. Xilinx Floor Planner)
Can help to remove critical paths, and greatly decrease tool running time

21. Route (Text: Chapter 17) Connect placed resources together
Two requirements
Design must be completely routed
Routed design meets timing requirements
Widely used algorithm “PathFinder”
PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs PathFinder (FPGA’95)
McMurchie and Ebeling
Reconfigurable Computing (Chapter 17)
Scott Hauch, Andre Dehon (2008)

22. Place & Route: How hard is it?
Let’s take a look at MP1’s layout

23. Configuration File Generation (Text: Chapter 19)
Convert place & routed design into a device configuration file (e.g. bitfile for Xilinx devices)
Download the configuration file to the FPGA

24. Next Class
Short History of Reconfigurable computing

25. Questions/Comments/Concerns
Write down
Main point of lecture
One thing that’s still not quite clear
If everything is clear, then give an example of how to apply something from lecture OR