1. Instructor: Dr. Phillip Jones
CPRE 583 Reconfigurable Computing Lecture 15: Fri 10/15/2010 (Reconfiguration Management)
Instructor: Dr. Phillip Jones
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA

2. Announcements/Reminders
Midterm:
Take home portion (40%) given Friday 10/22, due Tue 10/26 (midnight)
In class portion (60%) Wed 10/27
Distance students will have in class portion given via a timed WebCT (2 hour) session (take on Wed, Thur or Friday).
Start thinking of class projects and forming teams
Submit teams and project ideas: Mon 10/11 midnight
Project proposal presentations: Fri 10/22
MP3: PowerPC Coprocessor offload (today/tomorrow)
Problem 2 of HW 2 (released after MP3 gets released)

3. Initial Project Proposal Slides (5-10 slides)
Project team list: Name, Responsibility (who is project leader)
Team size: 3-4 (5 case-by-case)
Project idea
Motivation (why is this interesting, useful)
What will be the end result
High-level picture of final product
High-level Plan
Break project into mile stones
Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip.
System block diagrams
High-level algorithms (if any)
Concerns
Implementation
Conceptual
Research papers related to you project idea

4. Projects Ideas: Relevant conferences
FPL
FPT
FCCM
FPGA
DAC
ICCAD
Reconfig
RTSS
RTAS
ISCA
Micro
Super Computing
HPCA
IPDPS

5. Initial Project Proposal Slides (5-10 slides)
Project team list: Name, Responsibility (who is project leader)
Project idea
Motivation (why is this interesting, useful)
What will be the end result
High-level picture of final product
High-level Plan
Break project into mile stones
Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip.
System block diagrams
High-level algorithms (if any)
Concerns
Implementation
Conceptual
Research papers related to you project idea

6. Weekly Project Updates
The current state of your project write up
Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section
The current state of your Final Presentation
Your Initial Project proposal presentation (Due Fri 10/22). Should make for a starting point for you Final presentation
What things are work & not working
What roadblocks are you running into

7. Projects: Target Timeline
Teams Formed and Idea: Mon 10/11
Project idea in Power Point 3-5 slides
Motivation (why is this interesting, useful)
What will be the end result
High-level picture of final product
Project team list: Name, Responsibility
High-level Plan/Proposal: Fri 10/22
Power Point 5-10 slides
System block diagrams
High-level algorithms (if any)
Concerns
Implementation
Conceptual
Related research papers (if any)

8. Projects: Target Timeline
Work on projects: 10/ /8
Weekly update reports
More information on updates will be given
Presentations: Last Wed/Fri of class
Present / Demo what is done at this point
15-20 minutes (depends on number of projects)
Final write up and Software/Hardware turned in: Day of final (TBD)

9. Project Grading Breakdown
50% Final Project Demo
30% Final Project Report
30% of your project report grade will come from your 5-6 project updates. Friday’s midnight
20% Final Project Presentation

10. Common Questions

11. Common Questions

12. Overview
Chapter 4: Reconfiguration Management

13. What you should learn Some basic configuration architectures
Key issues when managing the reconfiguration of a system

14. Reconfiguration Management
Goal:
Minimize the overhead associated with run-time reconfiguration
Why import to address
Can take 100’s of milliseconds to reconfigure a device
For high performance applications this can be a large overhead (i.e. decreases performance)

15. High Level Configuration Setups
Externally trigger reconfiguration
CPU
Configuration
Request
FPGA
ROM
(bitfile)
Config Data
FSM
Config
Control
(CC)

16. High Level Configuration Setups
Self trigger reconfiguration
FPGA
Config Data
ROM
(bitfile)
FSM CC

17. Configuration Architectures
Single-context
Multi-context
Partially Reconfigurable
Relocation & Defragmentation
Pipeline Reconfiguration
Block Reconfigurable

18. Single-context FPGA Config clk Config I/F Config Data Config enable
OUT IN
OUT IN
OUT EN EN EN
Config enable

19. Multi-context FPGA 1 1 2 2 3 3 Config clk Context switch Config Config
OUT IN
OUT IN EN EN
Context switch 1 1
Context 1
Enable 2 2
Context 2
Enable 3 3
Context 3
Enable
Config
Enable
Config
Enable
Config Data
Config Data

20. Partially Reconfigurable
Reduce amount of configuration to send to device. Thus decreasing reconfiguration overhead
Need addressable configuration memory, as opposed to single context daisy chain shifting
Example Encryption
Change key
And logic dependent on key
PR devices
AT40K
Xilinx Virtex series (and Spartan, but not a run time)
Need to make sure partial config do not overlap in space/time (typical a config needs to be placed in a specific location, not as homogenous as you would think in terms of resources, and timing delays)

21. Partially Reconfigurable

22. Partially Reconfigurable
Full Reconfig
10-100’s ms

23. Partially Reconfigurable
Partial Reconfig
100’s us - 1’s ms

24. Partially Reconfigurable
Partial Reconfig
100’s us - 1’s ms

25. Partially Reconfigurable
Partial Reconfig
100’s us - 1’s ms

26. Partially Reconfigurable
Partial Reconfig
100’s us - 1’s ms

27. Partially Reconfigurable
Partial Reconfig
100’s us - 1’s ms
Typically a partial configuration modules map to a specific physical location

28. Relocation and Defragmentation
Make configuration architectures support relocatable modules
Example of defragmentation text good example (defrag or swap out, 90% decrease in reconfig time compared to full single context)
Best fit, first fit, …
Limiting factor
Routing/logic is heterogeneous
timing issues, need modified routes
Special resources needed (e.g. hard mult, BRAMS)
Easy issue if there are blocks of homogeneity
Connection to external I/O (fix IP cores, board restrict)
Virtualized I/O (fixed pin with multiple internal I/Fs?
2D architecture more difficult to deal with
Summary of feature PR arch should have
Homogenous logic and routing layout
Bus based communication (e.g. network on chip)
1D organization for relocation

29. Relocation and DefragmentationB C

30. Relocation and Defragmentation

31. Relocation and Defragmentation

32. Relocation and Defragmentation

33. Relocation and Defragmentation

34. Relocation and Defragmentation
More efficient use
of Configuration
Space C A

35. Pipeline Reconfigurable
Example: PipeRench
Simplifies reconfiguration
Limit what can be implemented
Cycle
Virtual
Pipeline
stage 1 2 3 4 PE PE PE PE 1 1 1 PE PE PE PE 2 2 2 3 3 3 PE PE PE PE 4 4
Cycle
Physical
Pipeline
stage 1 2 3 3 3 1 1 1 4 4 2 2 2

36. Block Reconfigurable Swappable Logic Units
Abstraction layer over a general PR architecture: SCORE
Config
Data

37. Managing the Reconfiguration Process
Choosing a configuration
When to load
Where to load
Reduce how often one needs to reconfigure, hiding latency

38. Configuration Grouping
What to pack
Pack multiple related in time configs into one
Simulated annealing, clustering based on app control flow

39. Configuration Caching
When to load
LRU, credit based dealing with variable sized configs

40. Configuration Scheduling
Prefetching
Control flow graph
Static compiler inserted conf instructions
Dynamic: probabilistic approaches MM (branch prediction)
Constraints
Resource
Real-time
Mitigation
System status and prediction
What are current request
Predict which config combination will give best speed up

41. Software-based Relocation Defragmentation
Placing R/D decision on CPU host not on chip config controller

42. Context Switching
Safe state then start where left off.

43. Next Lecture
Data Parallel

44. Questions/Comments/Concerns
Write down
Main point of lecture
One thing that’s still not quite clear
If everything is clear, then give an example of how to apply something from lecture OR

45. Lecture Notes