1. 1 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 23: Wed 11/16/2011 (High-level Acceleration Approaches) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ee.iastate.edu/cpre583/

2. 2 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) HW3: will be assigned as extra credit Exam 2 –Reminder push back to Friday after Thanksgiving week Weekly Project Updates due: Friday’s (midnight) Announcements/Reminders

3. 3 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Project Grading Breakdown 50% Final Project Demo 30% Final Project Report –20% of your project report grade will come from your 5-6 project updates. Friday’s midnight 20% Final Project Presentation

4. 4 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) FPL FPT FCCM FPGA DAC ICCAD Reconfig RTSS RTAS ISCA Projects Ideas: Relevant conferences Micro Super Computing HPCA IPDPS

5. 5 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Teams Formed and Topic: Mon 10/10 –Project idea in Power Point 3-5 slides Motivation (why is this interesting, useful) What will be the end result High-level picture of final product –Project team list: Name, Responsibility High-level Plan/Proposal: Fri 10/14 –Power Point 5-10 slides (presentation to class Wed 10/19) System block diagrams High-level algorithms (if any) Concerns –Implementation –Conceptual Related research papers (if any) Projects: Target Timeline

6. 6 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Work on projects: 10/19 - 12/9 –Weekly update reports More information on updates will be given Presentations: Finals week –Present / Demo what is done at this point –15-20 minutes (depends on number of projects) Final write up and Software/Hardware turned in: Day of final (TBD) Projects: Target Timeline

7. 7 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Initial Project Proposal Slides (5-10 slides) Project team list: Name, Responsibility (who is project leader) –Team size: 3-4 (5 case-by-case) Project idea Motivation (why is this interesting, useful) What will be the end result High-level picture of final product High-level Plan –Break project into mile stones Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip. –System block diagrams –High-level algorithms (if any) –Concerns Implementation Conceptual Research papers related to you project idea

8. 8 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Weekly Project Updates The current state of your project write up –Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section The current state of your Final Presentation –Your Initial Project proposal presentation (Due Wed 10/19). Should make for a starting point for you Final presentation What things are work & not working What roadblocks are you running into

9. 9 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Common Questions

10. 10 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Discuss some high-level approaches for accelerating applications. Overview

11. 11 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Start to get a feel for approaches for accelerating applications. What you should learn

12. 12 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Profiling Applications Finding bottlenecks Profiling tools –gprof: http://www.cs.nyu.edu/~argyle/tutorial.html http://www.cs.nyu.edu/~argyle/tutorial.html –Valgrind

13. 13 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining 4-LUT B C D A DFF 4-LUT DFF 4-LUT DFF 4-LUT DFF output 4-LUT B C D A DFF 4-LUT DFF 4-LUT DFF 4-LUT DFF 1 DFF delay per output How many ns to process to process 100 input vectors? Assuming each LUT Has a 1 ns delay. Input vector How many ns to process 100 input vectors? Assume a 1 ns clock

14. 14 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining (Systolic Arrays) Dynamic Programming 1.Start with base case Lower left corner 2.Formula for computing numbering cells 3. Final result in upper right corner.

15. 15 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining (Systolic Arrays) 1 Dynamic Programming 1.Start with base case Lower left corner 2.Formula for computing numbering cells 3. Final result in upper right corner.

16. 16 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining (Systolic Arrays) 1 11 Dynamic Programming 1.Start with base case Lower left corner 2.Formula for computing numbering cells 3. Final result in upper right corner.

17. 17 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining (Systolic Arrays) 1 12 111 Dynamic Programming 1.Start with base case Lower left corner 2.Formula for computing numbering cells 3. Final result in upper right corner.

18. 18 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining (Systolic Arrays) 13 123 111 Dynamic Programming 1.Start with base case Lower left corner 2.Formula for computing numbering cells 3. Final result in upper right corner.

19. 19 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining (Systolic Arrays) 136 123 111 Dynamic Programming 1.Start with base case Lower left corner 2.Formula for computing numbering cells 3. Final result in upper right corner.

20. 20 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining (Systolic Arrays) 136 123 111 Dynamic Programming 1.Start with base case Lower left corner 2.Formula for computing numbering cells 3. Final result in upper right corner. How many ns to process if CPU can process one cell per clock (1 ns clock)?

21. 21 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining (Systolic Arrays) 136 123 111 Dynamic Programming 1.Start with base case Lower left corner 2.Formula for computing numbering cells 3. Final result in upper right corner. How many ns to process if FPGA can obtain maximum parallelism each clock? (1 ns clock)

22. 22 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Pipelining (Systolic Arrays) 136 123 111 Dynamic Programming 1.Start with base case Lower left corner 2.Formula for computing numbering cells 3. Final result in upper right corner. What speed up would an FPGA obtain (assuming maximum parallelism) for an 100x100 matrix. (Hint find a formula for an NxN matrix)

23. 23 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Dr. James Moscola (Example) MATL 2 D 10 ML 9 MATP 1 IL 7 IR 8 END 3 E 12 IL 11 ROOT 0 MP 3 D6D6 MR 5 ML 4 S0S0 IL 1 IR 2 ROOT 0 MATP 1 MATL 2 END 3 1 2 3 c g a c g a 123

24. 24 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Example RNA Model MATL 2 D 10 ML 9 MATP 1 IL 7 IR 8 END 3 E 12 IL 11 ROOT 0 MP 3 D6D6 MR 5 ML 4 S0S0 IL 1 IR 2 ROOT 0 MATP 1 MATL 2 END 3 1 2 3 c g a c g a 123

25. 25 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Baseline Architecture Pipeline D 10 ML 9 IL 11 IR 8 IL 7 D6D6 MR 5 ML 4 MP 3 IR 2 IL 1 S0S0 E 12 resid ue pipeli ne ROOT 0 MATP 1 MATL 2 END 3 u g c gg acaccc

26. 26 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Processing Elements ML 4 j  d  + + + + = = = + IL 7,3,2 IR 8,3,2 ML 9,3,2 D 10,3,2 ML 4_t(10) ML 4_t(9) ML 4_t(8) ML 4_t(7) ML 4_e(A) ML 4_e(C) ML 4_e(G) ML 4_e(U) input residue, x i ML 4,3,3 =.22 0123 0 1 2 3.40-INF.22.72.30-INF.30.44-INF

27. 27 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Baseline Results for Example Model Comparison to Infernal software –Infernal run on Intel Xeon 2.8GHz –Baseline architecture run on Xilinx Virtex-II 4000 occupied 88% of logic resources run at 100 MHz –Input database of 100 Million residues Bulk of time spent on I/O (41.434s)

28. 28 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Expected Speedup on Larger Models Model Name Num PEs Pipeline Width Pipeline Depth Latency (ns) HW Processing Time (seconds) Total Time with measured I/O (seconds) Infernal Time (seconds) Infernal Time (QDB) (seconds) Expected Speedup over Infernal Expected Speedup over Infernal (w/QDB) RF00001353954539492195195001.000019542.434019534949212844382363027 RF00016548400243256282282001.000028242.434028233600018852179184443 RF00034318103838772187187001.000018742.43401873148368752074192062 RF00041424341544509206206001.000020642.434020638815611869291472797 Example812666001.000000642.434000610398682520 Speedup estimated... –using 100 MHz clock –for processing database of 100 Million residues Speedups range from 500x to over 13,000x –larger models with more parallelism exhibit greater speedups

29. 29 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Distributed Memory Cache ALU BRAM PE

30. 30 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Short Overview of Good Reference Achieving High Performance with FPGA-Based Computing –Reading #11 –Martin C. Herbordt, 2007

31. 31 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Next Class Evolvable Hardware

32. 32 - CPRE 583 (Reconfigurable Computing): High-level Acceleration Approaches Iowa State University (Ames) Questions/Comments/Concerns Write down –Main point of lecture –One thing that’s still not quite clear –If everything is clear, then give an example of how to apply something from lecture OR