HARDROC: Readout Chip for CALICE/EUDET Digital Hadronic calorimeter Nathalie Seguin-Moreau

TWEPP , Sept 22nd ASICs for CALICE/EUDET 2 « Imaging calorimetry » at ILC Particle flow algorithm –Reconstruct each particle individually –Bring jet resolution down to 30%/√E –Measure charged particles in tracker –Measure photons in ECAL –Measure hadrons in ECAL and HCAL –Minimize confusion term Calorimeter design –High granularity : typ < 1 cm 2 –High segmentation : ~30 layers –Moderate energy resolution (10%/√E) –ECAL : Silicon-Tungsten –HCAL : analog vs digital CALICE collaboration –« a high granularity calorimeter optimized for particle flow algorithm » –280 phys./eng., 11 countries, 42 labs ©J.C Brient (LLR) F. Sefkow (DESY)

TWEPP , Sept 22nd ASICs for CALICE/EUDET 3 CALICE physics prototypes 1 m 3 prototype for physics tests –Goal : study particle flow algorithm –Validate simulation and check performance of detectors in TB 3 calorimeters in testbeam (since 2003) –ECAL : W-Si 24X 0 20x20 cm 2 –AHCAL : Tiles + fibers + SiPMs –DHCAL : RPCs –Already 10 4 to channels ! –Run at DESY (05), CERN (06), FNAL (07 and 08) Moving since 2006 to large scale (1.5m) technological prototypes : « 2 nd generation ASICs and DAQ» –European funding « EUDET » –HaRDROC, SKIROC, SPIROC…

TWEPP , Sept 22nd ASICs for CALICE/EUDET 4 ROC chips for technological prototypes SPIROC Analog HCAL (AHCAL) (SiPM) 36 ch. 32mm² June 07 and June 08 HARDROC Digital HCAL (DHCAL) (RPC, µmegas or GEMs) 64 ch. 16mm² Sept 06 and June 08 SKIROC ECAL (Si PIN diode) 36 ch. 20mm² Nov 06 Requirements for electronics –Large dynamic range (15 bits) –Auto-trigger on ½ MIP –On chip zero suppress –Front-end embedded in detector –Ultra-low power : 25µW/ch –10 8 channels –Compactness « Tracker electronics with calorimetric performance » No chip = no detector !! ROC chips for technological prototype: to study the feasibility of large scale, industializable modules (Eudet funded) Poster 113, L. Raux

TWEPP , Sept 22nd ASICs for CALICE/EUDET 5 Read out: token ring Acquisition A/D conv.DAQIDLE MODE Chip 0 Chip 1 Acquisition A/D conv.DAQIDLE MODEIDLE Chip 2 Acquisition A/D conv.IDLE MODEIDLE Chip 3 Acquisition A/D conv.IDLE MODEIDLE Chip 4 Acquisition A/D conv.IDLE MODEIDLEDAQ 1ms (.5%).5ms (.25%) 1% duty cycle99% duty cycle 199ms (99%) Readout architecture common to all calorimeters –Daisy chain using token ring mode Minimize data lines & power 5 events3 events 0 event 1 event 0 event Chip 0Chip 1Chip 2Chip 3Chip 4 Data bus ILC beam Poster 114, F. Dulucq

TWEPP , Sept 22nd ASICs for CALICE/EUDET 6 DHCAL: Technological prototype Absorber: 40 steel plates of 20 mm (~1X0), gives 4λ Active medium: –Resistive plate chambers (RPC, led by I. Laktineh, IPN Lyon)) or µMEGAS (led by Y. Kariotakis and C. Adloff, LAPP Annecy) –High granularity : 1x1 cm 2 –High segmentation => channels for the entire HCAL –Semi digital readout per PAD to preserve single particle resolution FE Chip: HARDROC1 (Sept 06) and 2 (June 09), SiGe BiCMOS 0.35um, 64 channels ECAL DHCAL 100 GeV pions

TWEPP , Sept 22nd ASICs for CALICE/EUDET 7 HARDROC: HAdronic Rpc Digital ReadOut Chip Variable gain (8bits) current preamps (50 ohm input) One multiplexed analog output (12bit) 3 shapers, variable Rf,Cf and gains 3 thresholds (=> 3 DACs): 10 fC, 100fC, 1pC (megas) 100fC, 1pC, 10pC (GRPC) Auto-trigger on 10fC Store all channels and BCID for every hit. Depth = 128 bits Data format : 128(depth)*[2bit*64ch+24bit(BCID)+8bit (Header)] = 20kbits 872 SC registers, default config Power pulsing

TWEPP , Sept 22nd ASICs for CALICE/EUDET 8 Trigger path : fast shaper and DAC Charge injected in one channel: 100fC –Fsb0: Typically 2mV/fC (variable by a factor 10) Scurves performed by varying the DAC value (Threshold) –3 integrated DACs to deliver threshold voltages –Residuals within ±5 mV / 2.2V dynamic range. INL= 0.2% (2LSB) –2.1 mV/DAC Unit ie 1 fC/DAC Unit (fsb0) FSB0, Qinj=100fC FSB1 (0100), Qinj=1 pC FSB2 (0100), Qinj=10 pC

TWEPP , Sept 22nd ASICs for CALICE/EUDET 9 Trigger efficiency measurements Qinj=100fC pedestal FSB0, 100K, 100fF, G=144 NO decoupling cap. Before correction σ=±10%

TWEPP , Sept 22nd ASICs for CALICE/EUDET 10 Analog and Digital crosstalk No decoupling capacitors (on bias and reference voltages) Crosstalk ~1% –Well differentiated, capacitive like –Dominated by the input –No long distance crosstalk Coupling of discriminator to inputs through ground or substrate –Trigger on CH1 and look at analog signal on CH2 –8 mV coupling = 3 fC Can limit the minimum threshold (not in this case as similar to noise) Needs careful chip layout Discri coupling Trigger (ch1) Xtk on ch2

TWEPP , Sept 22nd ASICs for CALICE/EUDET 11 POWER CONSUMPTION PA 5.46mA DAC 0.84mA 3 FSB 12.3mA BG 1.2mA 3 Discris 7.3mA vddd2 0.4mA (=0 if 40MHz OFF) TOTAL 29mA Maximum available power: –10 µW/ch with 0.5% duty cycle –=> 640µW/3.5V=180 µA for the entire chip –OFF= Ibias _cell switched off during interbunch –29mAx3.3V≈100mW –1.5mW/ch –7.5 µW/ch with 0.5% duty cycle

TWEPP , Sept 22nd ASICs for CALICE/EUDET 12 Power pulsing: « Awake » time PWR ON FSB0 8 µs All decoupling capacitors removed PWR ON: ILC like (1ms,199ms) PP of the analog part: –Input signal synchronised on PWR ON –=> Awake time= 8 µs DAC output (Vth) Trigger 25 µs PWR ON Power pulsing of the DAC: –25 µs (slew rate limited)

TWEPP , Sept 22nd ASICs for CALICE/EUDET 13 On a GRPC Daisy chain measurement Readout frame: Header (8bits), then BCID (24bits), then 128 bits for trig0 and trig1 PCB board associated to both RPC and µMegas detectors PADs 1x1 cm 2

TWEPP , Sept 22nd ASICs for CALICE/EUDET 14 To validate the semi-digital electronics readout system in beam conditions (daisy chain,stability, efficiency, no external componant) TESTBEAM (CERN, 2008):

TWEPP , Sept 22nd ASICs for CALICE/EUDET 15 and efficiency measured for various types of RPCs  Multiplicity (Xtk detector) and efficiency measured for various types of RPCs Multiplicity and efficiency measurements © IPN Lyon 5 RPC planes of 32x8 cm2 in testbeam

TWEPP , Sept 22nd ASICs for CALICE/EUDET 16 Slab #1 Slab #2 Slab #3 DIF #1 DIF #2 DIF #3 GRPC TOWARDS A TECHNOLOGICAL PROTOTYPE Fully equipped large scalable detector: Tested in cosmics and in test beam at cern in summer 09

TWEPP , Sept 22nd ASICs for CALICE/EUDET 17 1m 2 in testbeam (CERN, Summer 2009) GRPC chamber Pads over (low) threshold 17 Up to 93% efficiency © IPNL

TWEPP , Sept 22nd ASICs for CALICE/EUDET 18 MICROMEGAS detector equipped with HR2 Two 32x48 pad ASU (Active Unit Sensor) 24 HARDROC2 chips A 1m 2 detector equipped with 144 HR2 chips to be tested in test beam this Autumn © LAPP Annecy

TWEPP , Sept 22nd ASICs for CALICE/EUDET 19 HR2 test DC levels, power consumption, Band Gap voltage 3 DACs linearity Memory test SC test Trigger efficiency measurements FSB0 Gain Correction ©R. Della Negra, IPNL ≈300 chips tested this summer (IPNL Lyon and LAL Orsay) to equip 1m 2 RPC and µmegas detectors

TWEPP , Sept 22nd ASICs for CALICE/EUDET 20 Conclusion Good performance for HARDROC –Low noise/Large dynamic range –Token-ring readout –Power pulsing Production foreseen in 2010 to equip technological prototypes 3rd generation chips still to come –All channels treated independantly WEB site: