EE141 Arithmetic Circuits 1 Chapter 14 Arithmetic Circuits Rev /12/2003 Rev /05/2003

EE141 Arithmetic Circuits 2 A Generic Digital Processor

EE141 Arithmetic Circuits 3 Building Blocks for Digital Architectures Arithmetic and Unit - Bit-sliced datapath(adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

EE141 Arithmetic Circuits 4 Intel Microprocessor Itanium has 6 integer execution units like this

EE141 Arithmetic Circuits 5 Bit-Sliced Design

EE141 Arithmetic Circuits 6 Itanium Integer Datapath Fetzer, Orton, ISSCC’02

EE141 Arithmetic Circuits 7 Adders

EE141 Arithmetic Circuits 8 Full-Adder (FA) Generate (G) = AB Propagate (P) = A  B Delete =A B

EE141 Arithmetic Circuits 9 Boolean Function of Binary Full-Adder CMOS Implementation

EE141 Arithmetic Circuits 10 Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A  B Delete =A B Can also derive expressions for S and C o based on D and P Propagate (P) = A  B Note that we will be sometimes using an alternate definition for

EE141 Arithmetic Circuits 11 Ripple-Carry Adder Worst-case delay is linear with the number of bits FA A 0 B 0 S 0 A 1 B 1 S 1 A 2 B 2 S 2 A 3 B 3 S 3 C i,0 C o (  C i,1 ) C o C o,2 C o,3 t d = O(N)t adder = (N-1)t carry + t sum Critical Path Propagation delay (or critical path) is the worst-case delay over all possible input patterns A= 0001, B=1111, trigger the worst-case delay A: 0  1, and B= 1111 fixed to set up the worst- case delay transition.

EE141 Arithmetic Circuits 12 Complimentary Static CMOS Full Adder Logic effort of Ci is reduced to 2 (c.f., A and B signals) Ci is late arrival signal  near the output signal Co needs to be inverted  Slow down the ripple propagate 28 Transistors

EE141 Arithmetic Circuits 13 Inversion Property

EE141 Arithmetic Circuits 14 Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property Reduce One inverter delay in each Full-adder (FA) unit

EE141 Arithmetic Circuits 15 A Better Structure: The Mirror Adder Exploring the “Self-Duality” of the Sum and Carry functions

EE141 Arithmetic Circuits 16 Mirror Adder: Stick Diagram

EE141 Arithmetic Circuits 17 Mirror Adder Design Mirror Adder Design The NMOS and PMOS chains are completely symmetrical A maximum of two series transistors can be observed in the carry-generation circuitry  for good speed. When laying out the cell, the most critical issue is the minimization of the capacitance at node C o. The capacitance at node C o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to C i are placed closest to the output.

EE141 Arithmetic Circuits 18 Transmission-Gate Full Adder (24T) Same delay for Sum and Carry  Multiplier design

EE141 Arithmetic Circuits 19 Manchester Carry-Chain Adder Static Circuits Dynamic Circuits

EE141 Arithmetic Circuits 20 Manchester Carry Chain

EE141 Arithmetic Circuits 21 Manchester Carry-Chain Adder

EE141 Arithmetic Circuits 22 Carry-Bypass Adder Also called Carry-Skip

EE141 Arithmetic Circuits 23 Carry-Bypass Adder (cont.) t adder = t setup + M tcarry + (N/M-1)t bypass + (M-1)t carry + t sum M bits form a Section  (N/M) Bypass Stages

EE141 Arithmetic Circuits 24 Carry Ripple versus Carry Bypass Wordlength (N) > 4~8 is better for Bypass Adder

EE141 Arithmetic Circuits 25 Carry-Select Adder

EE141 Arithmetic Circuits 26 Carry Select Adder: Critical Path

EE141 Arithmetic Circuits 27 Linear Carry Select

EE141 Arithmetic Circuits 28 Square Root Carry Select N-bit adder with P stages, 1 st stage adds M bits 

EE141 Arithmetic Circuits 29 Adder Delays - Comparison

EE141 Arithmetic Circuits 30 Look-ahead Adder - Basic Idea

EE141 Arithmetic Circuits 31 Look-Ahead: Topology Expanding Lookahead equations: All the way:

EE141 Arithmetic Circuits 32 Multipliers

EE141 Arithmetic Circuits 33 Binary Multiplication Binary Multiplication

EE141 Arithmetic Circuits 34 Binary Multiplication Binary Multiplication

EE141 Arithmetic Circuits 35 Array Multiplier

EE141 Arithmetic Circuits 36 MxN Array Multiplier — Critical Path Critical Path 1 & 2

EE141 Arithmetic Circuits 37 Carry-Save Multiplier

EE141 Arithmetic Circuits 38 Multiplier Floorplan

EE141 Arithmetic Circuits 39 Wallace-Tree Multiplier

EE141 Arithmetic Circuits 40 Wallace-Tree Multiplier

EE141 Arithmetic Circuits 41 Wallace-Tree Multiplier

EE141 Arithmetic Circuits 42 Multipliers —Summary Identify Critical Paths Other Possible techniques: Data Encoding (Booth) Logarithmic v.s. Linear (Wallace Tree Multiplier) Pipelining

EE141 Arithmetic Circuits 43 Shifters

EE141 Arithmetic Circuits 44 The Binary Shifter

EE141 Arithmetic Circuits 45 The Barrel Shifter Area Dominated by Wiring

EE141 Arithmetic Circuits 46 4x4 barrel shifter Width barrel ~ 2 p m M

EE141 Arithmetic Circuits 47 Logarithmic Shifter

EE141 Arithmetic Circuits 48 A 3 A 2 A 1 A 0 Out3 Out2 Out1 Out0 0-7 bit Logarithmic Shifter

EE141 Arithmetic Circuits 49 Summary  Datapath designs are fundamentals for high- speed DSP, Multimedia, Communication digital VLSI designs.  Most adders, multipliers, division circuits are now available in Synopsys Designware under different area/speed constraint.  For details, check “Advanced VLSI” notes, or “Computer Arithmetic” textbooks