1. S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 25: Datapath Subsystems 1/4 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. S. Reda EN1600 SP’08 Datapath Subsystems  Adders  Multipliers  Comparators  Counters  Shifters

3. S. Reda EN1600 SP’08 Adders Addition is the most commonly used arithmetic operation → could be speed limiting → optimization of the adder is of the utmost importance

4. S. Reda EN1600 SP’08 A N-bit carry-ripple adder can be constructed by cascading 1-bit FA Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit t d = O(N) t adder = (N-1)t carry + t sum

5. S. Reda EN1600 SP’08 Full adder Boolean equations S can be factored to reuse the C o term

6. S. Reda EN1600 SP’08 An implementation that requires 28 transistors

7. S. Reda EN1600 SP’08 Problems with the design Problems: Large area Tall transistor stacks Large intrinsic capacitance for C o Note C i is connected to the transistor closest to the output

8. S. Reda EN1600 SP’08 Self-dual property of FAs Self duality enables two optimizations: A.PGK mirror FA B.Faster ripple carry adder A.A full adder receiving complementary inputs produce complementary outputs B. An inverting full adder receiving complementary inputs produce true outputs

9. S. Reda EN1600 SP’08 A. PGK mirror FA design For a full adder, define what happens to carry –Generate: C out = 1 independent of C G = A B –Propagate: C out = C P = A  B –Kill: C out = 0 independent of C K = ~A ~B

10. S. Reda EN1600 SP’08 A. The mirror adder  Still need two inverters to generate Co and S V DD C i A B BA B A A B Kill Generate "1"-Propagate "0"-Propagate V DD C i AB C i C i B A C i A B B A V S C o Less area Shorter stacks Less intrinsic capacitance

11. S. Reda EN1600 SP’08 A. Mirror adder stick diagram

12. S. Reda EN1600 SP’08 B. Minimize critical path (carry) by reducing the number of inverters along the path FA’ is a FA without the inverter in the carry path A 3 FA Even cellOdd cell FA A 0 B 0 S 0 A 1 B 1 S 1 A 2 B 2 S 2 B 3 S 3 C i,0 C o C o,1 C o,3 C o,2,,,,