4 May 2006May 06 PMG - Paul R1 AFEII-t Status May 4, 2006 PMG Paul Rubinov

4 May 2006May 06 PMG - Paul R2 Outline  Past  TriP-t testing  Tests of the pre - production boards on platform  Production Readiness Review  Present  Production status  Schedule  Platform testing  Future  Testing  Installation and Commissioning

4 May 2006May 06 PMG - Paul R3 Past Trip-t testing DONE : 350 boards + 9.2% spares (6115) Direct your gratitude to Leo Bellantoni for making this slide so short!

4 May 2006May 06 PMG - Paul R4 Past Testing of AFEII-t boards on platform  Some done, more to do 1.Took data with one AFEII-t prototype AND one pre- production before shutdown. (3 stores in all) 2.LED spectra, calibrations, readout testing during shutdown. u Summary so far: Every part of the AFEII-t is known to “work” Now it all needs to work at the same place at the same time

4 May 2006May 06 PMG - Paul R5 Past AFEII-t boards known to work  Mechanical: Interface to cassette, backing bars, alignment pins, springs, handles, [air dams]  Backend: Interface to Sequencer readout (a.k.a. grey cable), interface to Central Track Trigger (a.k.a. LVDS), power supplies, 1553  Bottom: Analog performance (big signals and small signals, analog and discriminators), bias, temperature control  Front: Firmware (readout format, personality), software, calibration, reliability, stability

4 May 2006May 06 PMG - Paul R6 Is it safe?  To make 350 AFEII-t ?

4 May 2006May 06 PMG - Paul R7 Still past  Production Readiness Review  A collection of EEs and Phys from Dzero  Most of the presentation focused on the readout problems  Asked some tough questions  Readout issues  Test for CPS dynamic range  Test for CTT link diagnostics and timing  Reliability, manufacturability: lead free issues, via issues

4 May 2006May 06 PMG - Paul R8 Almost the present  Production Readiness Review bottom line  Boards approved  Boards ordered  Johnny Green and Tom Fitzpatrick sent to scout out the facility  Extra $7K spent to accelerate production as much as possible  (which as usual just covered schedule slippage)

4 May 2006May 06 PMG - Paul R9 Present  First 4 bare boards delivered to Millennium (our assembler) on May 2 nd  These will be used to profile the ovens and debug the pick and place programs  Expect to be ready to start rolling the boards 3 rd week of May  Expect 100 more boards to ship from Merix to Millennium 3 rd week of May Only the finest “Just In Time” for us!

4 May 2006May 06 PMG - Paul R10 Present  Schedule My top 3 priorities: 1. Meet the schedule 2. Meet the milestone 3. Meet the milestone on schedule “203 AFEII-t boards fully tested, working and ready to install”

4 May 2006May 06 PMG - Paul R11 Schedule  First bare boards – 1 st week May  First stuffed boards – 2 nd week of June  Millennium to make minimum 40 boards/week: 9 weeks – 2 nd week of Aug project complete.  Tested good means:  Flash/FPGAs programmed  EVERY channel injected with 2 amplitudes and peds and checked for ped, noise, gain  EVERY discriminator fires/doesn’t fire for the correct threshold  LVDS links checked  Temperature control circuitry checked and calibrated  Bias setting and readback checked and calibrated

4 May 2006May 06 PMG - Paul R12 Present platform testing  3 objectives for shutdown remain  Run temperature control on platform using the automatic calibration procedure  as of May 3rd  Tune the AFEII to CTT timing  Take cosmic ray data with CPS so we have a MIP calibration before beam returns

4 May 2006May 06 PMG - Paul R13 Future  Testing  Testing personnel accounted for – tests are fairly fast and automated, so not an issue.  General outline of the testing plan worked out, software nearly done, procedures being developed.  1 bench top test stands 100% ready to go – being used to develop testing procedures  2 bench top test stands ready except for LVDS (waiting for cables)  Phase V now able to calibrate AFEII-t for temperature and bias at the push of a button!

4 May 2006May 06 PMG - Paul R14 Future  Testing Plan 1.Inspect and do the final board assembly, enter into tracking database. (1hr) 2.Program board and run it through automated bench top test procedure. (30 min) 3.Run board through Phase V. (30 min) 4.Install board into Combined Test Stand for burn in (24 hrs, but there are 16 slots)

4 May 2006May 06 PMG - Paul R15 Future  Installation and commissioning plans for the boards are currently being refined.  General strategy:  Put them where we know they work, study them there (e.g. use the stereo boards to study the performance and calibration of the discriminators)  Put them where they will do the most good (CPS because of saturation problems, sectors with longest wave guides = smallest signals)  Put them where it will be easy to see the effect (so concentrate in one sector)

4 May 2006May 06 PMG - Paul R16 First batch

4 May 2006May 06 PMG - Paul R17 Crate locations

4 May 2006May 06 PMG - Paul R18 Conclusion  Prototype phase is done  Pre production phase is (almost) done  Production has started  Testing is being setup  Project completion projected for mid August

4 May 2006May 06 PMG - Paul R19 Pretty pictures Same spot on detector pulsed by LED AFE1 – left plot AFEII – right plot (2 out of 64 plots shown)

4 May 2006May 06 PMG - Paul R J. Warchol 20 AFE 1 and AFE 2 have the same analog gain Run (AFE1), (AFE2) AFE 1 AFE 2

4 May 2006May 06 PMG - Paul R J. Warchol 21 AFE 1, CFT axial discriminator off, discriminator on Runs ,

4 May 2006May 06 PMG - Paul R J. Warchol 22 AFE 2, CFT stereo discriminator off, discriminator on Run ,216934

4 May 2006May 06 PMG - Paul R J. Warchol 23 Discriminator Study: 50 % point distribution New firmware, board 13A4 RMS=1.5 SVX0 TriP #0 SVX0 TriP #1 SVX1 TriP #0 SVX1 TriP #1

4 May 2006May 06 PMG - Paul R J. Warchol 24 New firmware, board 13A4, SVX2, TriP #1

4 May 2006May 06 PMG - Paul R J. Warchol 25 New firmware, board 13A4, SVX2, TriP #1 Fifty % point, discr threshold 250 or 255 RMS 1.2 RMS 1.3

4 May 2006May 06 PMG - Paul R J. Warchol 26 LEDs on, rms of pulse height distribution vs VLPC pixel # AFEII #20 in 5A6 This proves AFEII readout mapping is correct AFE1 AFEII

4 May 2006May 06 PMG - Paul R27