1. Static Timing Analysis - II Sushant SinghSushant Singh

2. RECAP: Setup check with Ideal clock

3. Insertion of Clock Tree : Non - ideal Clocks

4. What are real clocks: Clock Tree is an essential process to minimize skew in the design. Clock Tree is an essential process to minimize skew in the design. Whenever Clock Tree is inserted, clock path becomes real. We also have network launch insertion delay and capture insertion delay. Whenever Clock Tree is inserted, clock path becomes real. We also have network launch insertion delay and capture insertion delay. All the timing parameters (Ghz) should be satisfied with real clocks. The chip should run at the specified frequency despite additional constraints. All the timing parameters (Ghz) should be satisfied with real clocks. The chip should run at the specified frequency despite additional constraints.

5. Modification of Clock Path:

7. Clock Network Delay shifts the edges:

8. Skew should be zero:

9. Setup Constraints with real clocks:

10. Data Arrival and Data Required Time:

12. Adding speed breakers (x): degrades Slack

13. Solving a local problem might adversely affect globally

14. Increasing DRT affects DAT in the next cycle: Increasing number of buffers in the capture clock increases DRT and helps DAT to meet timing (increasing slack). Increasing number of buffers in the capture clock increases DRT and helps DAT to meet timing (increasing slack). But it degrades the DAT or slack of the next clock cycle. But it degrades the DAT or slack of the next clock cycle. Be sure to check timing (slack) of the next cycle before adding buffers to meet timing of the current clock path. Be sure to check timing (slack) of the next cycle before adding buffers to meet timing of the current clock path. Solving constraints locally might adverse the timing globally. Solving constraints locally might adverse the timing globally.

15. Hold Analysis revisited for single clock:

16. Hold vs Setup Check: Recall that hold check is done on the same edge at both launch and capture flops. Recall that hold check is done on the same edge at both launch and capture flops. Setup check is done on different edges at both flops. Setup check is done on different edges at both flops. Hold failure leads to functional failure and setup check leads to incorrect capture of data or metastability. Hold failure leads to functional failure and setup check leads to incorrect capture of data or metastability.

17. Hold Time constraints with Real clocks:

18. Adding Necessary Hold Time constraints (pessimism):

19. Increasing slack in Hold Timing Constraints:

20. Increasing skew leads to increase in DRT, which results in Hold timing violation.