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CS 140 Lecture 11 Sequential Networks: Timing and Retiming Professor CK Cheng CSE Dept. UC San Diego 1

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Sequential Networks Timing: Setup Time and Hold Time Constraints D QQQQ CLK 2

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Combinational CLK A BC A typical sequential network has both a combinational circuit and flip-flips. D Sequential Networks 3

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Combinational CLK A BC t cq + t comb + t setup < T t hold < t cq + t comb Clock period Shortest path 4

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Input Timing Constraints Setup time: t setup = time before the clock edge that data must be stable (i.e. not changing) Hold time: t hold = time after the clock edge that data must be stable Aperture time: t a = time around clock edge that data must be stable (t a = t setup + t hold ) 5

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Output Timing Constraints Propagation delay: t pcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) Contamination delay: t ccq = time after clock edge that Q might be unstable (i.e., start changing) 6

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Dynamic Discipline The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements 7

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Setup Time Constraint The setup time constraint depends on the maximum delay from register R1 through the combinational logic. The input to register R2 must be stable at least t setup before the clock edge. T c t pcq + t pd + t setup t pd T c – (t pcq + t setup ) 8

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Hold Time Constraint The hold time constraint depends on the minimum delay from register R1 through the combinational logic. The input to register R2 must be stable for at least t hold after the clock edge. t hold < t ccq + t cd t cd > t hold - t ccq 9

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Timing Analysis Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps t pd = 35 ps t cd = 25 ps t pd = t cd = Setup time constraint: T c f c = 1/T c = Hold time constraint: t ccq + t pd > t hold ? 10

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Timing Analysis Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps t pd = 35 ps t cd = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 25 ps Setup time constraint: T c (50 + 105 + 60) ps = 215 ps f c = 1/T c = 4.65 GHz Hold time constraint: t ccq + t pd > t hold ? (30 + 25) ps > 70 ps ? No! 11

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Fixing Hold Time Violation Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps t pd = 35 ps t cd = 25 ps t pd = t cd = Setup time constraint: T c f c = Hold time constraint: t ccq + t pd > t hold ? Add buffers to the short paths: 12

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Fixing Hold Time Violation Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps t pd = 35 ps t cd = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 2 x 25 ps = 50 ps Setup time constraint: T c (50 + 105 + 60) ps = 215 ps f c = 1/T c = 4.65 GHz Hold time constraint: t ccq + t pd > t hold ? (30 + 50) ps > 70 ps ? Yes! Add buffers to the short paths: 13

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Clock Skew The clock doesnt arrive at all registers at the same time Skew is the difference between two clock edges Examine the worst case to guarantee that the dynamic discipline is not violated for any register – many registers in a system! 14

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Setup Time Constraint with Clock Skew In the worst case, the CLK2 is earlier than CLK1 T c t pcq + t pd + t setup + t skew t pd T c – (t pcq + t setup + t skew ) 15

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Hold Time Constraint with Clock Skew In the worst case, CLK2 is later than CLK1 t ccq + t cd > t hold + t skew t cd > t hold + t skew – t ccq 16

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Timing and Retiming Retiming: Adjust the clock skew so that the clock period can be reduced. Add a few more examples on timing and retiming. 17

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CS 140 Lecture 9 Professor CK Cheng 10/24/02. Sequential Network 1.Components F-Fs 2.Specification D Q Q’ CLK.

CS 140 Lecture 9 Professor CK Cheng 10/24/02. Sequential Network 1.Components F-Fs 2.Specification D Q Q’ CLK.

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