1. A 20/30 Gbps CMOS Backplane Driver with Digital Pre-emphasis Paul Westergaard, Timothy Dickson, and Sorin Voinigescu University of Toronto Canada

2. Outline Motivation Design Goals Circuit Description and Design Experimental Results Summary and Conclusion

3. Motivation Application Serial inter-chip communications over backplanes at 20-Gb/s. Unfulfilled Needs CMOS implementation over 10-Gbps > 30 dB dynamic range, low-power Programmable width and height pre- emphasis to increase receiver simplicity Prior Art Previous CMOS backplane drivers have only achieved 10 Gb/s data rate.

4. Design Goals 30-Gb/s main path operation without pre-emphasis 20-Gb/s fully featured operation with –‘digital’ pre-emphasis –eye-crossing –output swing control High Sensitivity (<10 mVpp per side) Large output swing (>350 mVpp per side) 50-Ohm input/output matching 1.5 V supply 130 nm CMOS implementation

5. Circuit Design and Description

6. Biasing for peak f T and NF MIN Peak f T bias 0.3mA/um Min. NF MIN 0.15mA/um Multi-stage amplifiers with signal path transistors biased at half peak fT

7. Circuit Architecture Multi-stage amplifier implementation Input stage biased and sized for high gain and low noise Inductive broad-banding in every inverter stage to reduce power and increase speed Main (higher-speed) and pre- emphasis paths are parallelized

8. Block Diagram

9. Input Matching and Low-Noise Comparator

10. Eye-crossing Control *D. S. McPherson, S. Voinigescu et al IEEE GaAs IC Symp. - Oct. 2002

11. Digital Pre-emphasis Delay Circuit

12. Digital Differentiator

13. Inductor design considerations Inductor broadband “2-  ” model model extracted for design from ASITIC simulations. Multi-layer ( 2 or 3 metals) design used to minimize inductor area (400, 700, 900 pH used) Largest inductor side is 44 um (900 pH)

14. Experimental Results

15. Chip Photograph

16. Input/Output Return Loss

17. Measured Eye-diagrams: 0.3Vp-p output 20 Gb/s 25 Gb/s 30 Gb/s

18. Sensitivity 20 Gb/s30 Gb/s Input: 21mVpp one side only Output: 80mVpp per side

19. 20-Gbs Eye with Pre-emphasis

20. Output Swing Control @20Gbps Input: 200mVpp one side only Output: 170mVppOutput: 340mVpp

21. Output Swing Control @30 Gbps Output: 170mVppOutput: 270mVpp (Gain at 30 Gb/s!) Input: 200mVpp one side only

22. 30%-70% Crossing Control @20 Gbs 70%30% 50%

23. 40%-60% Crossing Control @ 25 Gbs 60%40% 50%

24. Summary and Conclusion

25. Performance Summary ParameterMeasured val. Technology130nm CMOS Supply Voltage1.5 V Power Dissipation150 mW Output Swing @ 20 Gb/s170-350 mVp-p Pre-emphasis @ 20 Gb/s30%/10% Crossing Control @ 20Gb/s30% to 70% Eye sensitivity @ 20 Gb/s20(10) mVpp Dynamic Range @ 20 Gb/s 30 dB Noise Figure(10GHz,15GHz)16.5 dB, 17 dB S11/S22 up to 50 GHz<-12 dB

26. Conclusion First CMOS driver above 20 Gb/s Novel digital pre-emphasis High sensitivity, dynamic range Large output swing Eye-crossing control Communications between chips and backplanes is feasible at 20 Gb/s in 130-nm CMOS technology

27. Acknowledgements Rudy Beerkens and Boris Prokes of STMicroelectronics Ottawa STMicroelectronics for fabrication Micronet and Gennum Corporation for financial support Quake Technologies for access to 40 Gb/s BERT