1. 6-k 43-Gb/s Differential Transimpedance-Limiting Amplifiers with Auto-zero Feedback and High Dynamic Range H. Tran 1, F. Pera 2, D.S. McPherson 1, D. Viorel 1, and S.P. Voinigescu 3 1) Quake Technologies, Inc. Ottawa, ON, K2K 2T8, Canada 2) now with Insyte Corporation, Ottawa, ON, K2K 3C9, Canada 3) ECE Dept., University of Toronto, Toronto, ON, M5S 3G4, Canada

2. Wednesday, November 12, 2003Slide 2M3 Outline Overview Broadband low-noise amplifier topologies and design methodology Circuit design and features Measurement results Summary

3. Wednesday, November 12, 2003Slide 3M3 Low-noise broadband amplifier topology Goals Minimize noise when circuit operated as TIA with 60-fF photodiode and As 50- voltage preamplifier As 50- voltage preamplifier Maximise dynamic range by using on-chip active feedback that does not degrade overall noise.

4. Wednesday, November 12, 2003Slide 4M3 Low-noise broadband topology choices EF-input stages have series feedback which increases noise impedance and results in very high noise figure. EF+INV or EF+Cherry-Hooper EF+INV or EF+Cherry-Hooper Inverter Inverter Differential TIA Differential TIA

5. Wednesday, November 12, 2003Slide 5M3 Noise figure topology analysis Diff. INV stage with on-chip 50 resistors has low-to- moderate noise but poor broadband S 11 F(Z 0 = 50 ) = 1 + [1 + ( L F /Z 0 ) 2 ] -1 + G nt Z 0 + R nt Z 0 (Y cort + 2/Z 0 ) 2 where: G nt = G 2 L EOPT, Y cort = jB L EOPT and R nt = R/L EOPT Diff. TIA stage matched to 50 offers lowest noise and broadband S 11 matching F(Z 0 ) = 1 + (Z 0 /R F )[1+( L F /R F ) 2 ] -1 + G nt Z 0 + R nt Z 0 (Y cort + 1/Z 0 +1/R F ) 2 If R F =Z 0 the two stages have identical Noise Figure.

6. Wednesday, November 12, 2003Slide 6M3 Transistor sizing for noise impedance Inverter input stage with matching 50- resistors has moderate transistor size (l EOPT ) and bias current. l EOPT = [2/( Z 0 )][R/(G + RB 2 )] 1/2 TIA stage matched to 50 offers lowest size (since R F > Z 0 ) and bias current. l EOPT = (1/ R F Z 0 )][R/(G + RB 2 )] 1/2 where R, G, B are technology-specific noise parameters

7. Wednesday, November 12, 2003Slide 7M3 TIALA specifications 200.. 400 mV p-p per side Adjustable output amplitude Adjustable input slicing level Signal level monitor 50 On-chip terminated outputs 450 mW DC power dissipation 3.3 V Single-supply pp to mA pp Dynamic range (BER<10 -1 6 k (40 dB) Differential T z /(power) gain

8. Wednesday, November 12, 2003Slide 8M3 TIALA block diagram

9. Wednesday, November 12, 2003Slide 9M3 TIA stage schematics

10. Wednesday, November 12, 2003Slide 10M3 Peak detector and output stage

11. Wednesday, November 12, 2003Slide 11M3 DC auto-zero feedback stage

12. Wednesday, November 12, 2003Slide 12M3 Chip microphotograph Fabricated by HRL- Laboratories 1 m, 160-GHz InP/InGaAs HBT process Substrate height of 100 m Two metal layers MIM capacitors Metal resistors 70- CPWs for isolation 1.8 mm 1 mm

13. Wednesday, November 12, 2003Slide 13M3 On-wafer DC output offset measurements Output differential DC- offset less than 40 mV pp for entire range of input DC current

14. Wednesday, November 12, 2003Slide 14M3 On-wafer S-parameter measurements TIA BW 3dB 38 GHz TIA T z gain540 TIA T z gain540 TIALA BW 3dB 36 GHz TIALA S 21 40 dB Isolation > 50 dB S 11 < -15 up to 50 GHz S 22 < -10 up to 50 GHz

15. Wednesday, November 12, 2003Slide 15M3 On-wafer measured sensitivity and monitor

16. Wednesday, November 12, 2003Slide 16M3 On-wafer 43-Gb/s eye-diagrams 43-Gb/s, 2 31 -1 differential output eye-diagram with 4.5-mA pp input. 43-Gb/s, 2 31 -1 differential output eye- diagram with 250- A pp input.

17. Wednesday, November 12, 2003Slide 17M3 As 43-Gb/s Limiting Amplifier in Module 43-Gb/s, 2 31 -1 input eye-diagram with 8-mV pp input signal level. Error-free 43-Gb/s, 2 31 -1 output eye- diagram with 8-mV pp input signal level and 300-mV pp output swing.

18. Wednesday, November 12, 2003Slide 18M3 Summary A high dynamic range TIALA with on-chip auto-zero feedback was designed and fabricated in InP/InGaAs HBT technology The input stage topology and design were optimized for broadband noise and input-impedance matching Signal monitor and slicing level adjust functions are incorporated The result is a unique circuit, with record functionality, that also operates as a 43-Gb/s, 50- matched voltage preamp or LA with record-breaking 8-mV pp sensitivity

19. Wednesday, November 12, 2003Slide 19M3 Acknowledgment The authors would like to thank HRL-Laboratories for fabricating the die They would also like to express their gratitude to Quake colleagues M. Tazlauanu and S. Szilagyi for their valuable contributions

20. Wednesday, November 12, 2003Slide 20M3 Limiting stage schematics

21. Wednesday, November 12, 2003Slide 21M3 Design overview On-chip auto-zero feedback for increased dynamic range Simultaneous noise- and input-impedance matching TIA and 2nd. gain stage operate in linear mode Output stages operate in limiting mode Signal level monitor, slicing level adjust, and output swing control functions Based on a 1- m InP/InGaAs technology

22. Wednesday, November 12, 2003Slide 22M3 TIA stage design methodology Transistors biased @ 0.6 mA/ m 2 for minimum noise figure at 36 GHz, not for maximum gain/bandwidth Transistors sized such that the optimal noise impedance with feedback is close to 50 Transistors sized such that the optimal noise impedance with feedback is close to 50 Inductors deployed in feedback network rather than in series with the loads for: improving S 11 over broader bandwidth, 3-dB bandwidth extension, and HF noise filtering.

23. Wednesday, November 12, 2003Slide 23M3 Setup for on-wafer eye measurements Anritsu MP1801A 43.5G Mux 86100A scope & 83484A 50 GHz mod. 12 flexible 2.4 mm cables 65 GHz GGB MCW with 150 m pitch 20 dB attenuator 60 flexible 2.4 mm cable for clock sync.

24. Wednesday, November 12, 2003Slide 24M3 Bandwidth of measurement setup BW = 16 GHz

25. Wednesday, November 12, 2003Slide 25M3 40 Gb/s eye-diagram (test setup) T r = 12.7 ps T f = 11.9 ps T j = 6.7 ps