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T. Chalvatzis, University of Toronto - ESSCIRC 20062 Outline Motivation Decision Circuit Design Measurement Results Summary

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T. Chalvatzis, University of Toronto - ESSCIRC 20063 Motivation Low-power, high-speed blocks in CMOS for mm- wave A/D Conversion [Chalvatzis, et al., RFIC2006] Low-power blocks for 40- Gb/s wireline and fiber-optic transceivers in CMOS

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T. Chalvatzis, University of Toronto - ESSCIRC 20064 Decision Circuit Block Diagram Two latches in Master-Slave configuration Data and clock amplifiers as TIAs Output driver buffers to 50Ω

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T. Chalvatzis, University of Toronto - ESSCIRC 20065 Conventional Latch Conventional CML latch requires 3 vertically stacked transistors Standard 1.2V supply in 90nm V DS too low for 40 Gb/s speed

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T. Chalvatzis, University of Toronto - ESSCIRC 20066 Previous Work To operate from lower power supply (<1.2V) Transformer coupling for clock-to-data path [Kehrer, et al., CSICS2004] -> Not broadband due to transformer Remove current sources [Kanda, et al., ISSCC2005] -> Not sufficient for 40Gb/s operation

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T. Chalvatzis, University of Toronto - ESSCIRC 20067 Proposed Latch Bias at peak-f T current density I BIAS =I peak-fT /2=0.15mA/μm High-V T devices on clock path Low-V T devices on data path For I BIAS =4.5mA and R L =40Ω: ΔV=9mAx40Ω=360mV Total power consumption: 10.8 mW/latch

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T. Chalvatzis, University of Toronto - ESSCIRC 20068 Retiming DFF – Schematic

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T. Chalvatzis, University of Toronto - ESSCIRC 20069 Retiming DFF – Schematic Clock must fully switch M1/M2 V DS,M7/8 swings as low as V T (M1/M2) Use high-V T for M1/M2 V DS,M7/8 =V DD -ΔV swing =V T =0.34V

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T. Chalvatzis, University of Toronto - ESSCIRC 200610 TIA Design Methodology Bias at min noise current density 0.15 mA/μm [Dickson, et al., JSSC Aug 2006] p-MOS active load to increase gain at low V DD Feedback inductor L F resonates out the capacitance at the TIA node L F =500pH designed with two top metals for minimum footprint to obtain high SRF

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T. Chalvatzis, University of Toronto - ESSCIRC 200611 TIA scaling to 65-nm CMOS TIA BW 3dB =28GHz @ 3mA

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T. Chalvatzis, University of Toronto - ESSCIRC 200612 Fabrication and measurement results of decision circuit

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T. Chalvatzis, University of Toronto - ESSCIRC 200613 P=130mW @ V DD =1.2V Area=600x800μm 2 Circuit fabricated in two different foundries TIA DFFDRIVER CLOCK TREE Decision Circuit – Die Photo

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T. Chalvatzis, University of Toronto - ESSCIRC 200614 Retiming DFF – Test Setup 40-Gb/s signal generated from 4x10Gb/s streams Solid linesData signals Dashed linesClock signals

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T. Chalvatzis, University of Toronto - ESSCIRC 200615 Measurements at 30Gb/s FCLK=30GHz, Data Rate=30Gb/s, Trise=7ps JitterRMS,input=1.7psJitterRMS,output=0.5ps Single-ended input with other input terminated to 50Ω Jitter from setup not de-embedded Input (top) Output (Bottom)

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T. Chalvatzis, University of Toronto - ESSCIRC 200616 Measurements at 30Gb/s vs V DD, T JitterRMS,input=1.7psJitterRMS,input=1.4ps JitterRMS,output=0.7psJitterRMS,output=1.0ps Input (top) Output (Bottom) V DD =1V, T=25 o C V DD =1.2V, T=100 o C

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T. Chalvatzis, University of Toronto - ESSCIRC 200617 Measurements at 37Gb/s and 40Gb/s JitterRMS,input=1.292psJitterRMS,input=1.403ps JitterRMS,output=1.149psJitterRMS,output=1.396ps Input (top) Output (Bottom) 37Gb/s @ 1.2V40Gb/s @ 1.5V

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T. Chalvatzis, University of Toronto - ESSCIRC 200618 Measurements at 40Gb/s and 1.5V Error-free 508-bit pattern Input (top), output (bottom)

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T. Chalvatzis, University of Toronto - ESSCIRC 200619 Comparison of high-speed latches RefTechnologyRate (Gb/s) Supply (V) P LATCH (mW) P DEC,CIRC (mW) [3]245-GHz InP HEMT805.7N/A1200 [4]250-GHz InP HBT501.520125 [8]150-GHz SiGe BiCMOS432.523288 This work 120-GHz CMOS 37 40 1.2 1.5 10.8 20 130 240

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T. Chalvatzis, University of Toronto - ESSCIRC 200620 Conclusion 90-nm CMOS latch and retimer demonstrated at 37 Gb/s from 1.2 V and 40 Gb/s from 1.5 V supply p-MOS device for low-noise TIA on data and clock path Peak-f T bias and combination of low and high-V T devices in latch allows for 40-Gb/s retiming 1.2-V operation at 40 Gb/s possible if clock path TIA replaced with a CML inverter chain with inductive peaking and source follower

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T. Chalvatzis, University of Toronto - ESSCIRC 200621 Acknowledgements Nortel Networks for funding support STMicroelectronics and TSMC for chip fabrication ECTI, OIT and CFI for equipment NIT for lab access CMC for CAD tools

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T. Chalvatzis, University of Toronto - ESSCIRC 200622 Backup Slides

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T. Chalvatzis, University of Toronto - ESSCIRC 200623 f T of LVT and HVT transistors

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T. Chalvatzis, University of Toronto - ESSCIRC 200624 Measurements at 30Gb/s (min. input) Input (top) – Output (bottom) 30Gb/s @ 1.2V and 60mV input (13-dB attenuation) Retiming with JitterRMS,input=1.9ps JitterRMS,output=1.7ps

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T. Chalvatzis, University of Toronto - ESSCIRC 200625 Measurements at 7.5Gb/s (Fclk/4) Input (bottom) – Output (top). 7.5Gb/s @ 1.2V Retiming with JitterRMS,input=4.2ps JitterRMS,output=2.6ps

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