1. Unit 13 Analysis of Clocked Sequential Circuits Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2. 22004/05/24Analysis of Clocked Sequential Circuits Outline 13.1A Sequential Parity Checker 13.2Analysis by Signal Tracing and Timing Charts 13.3 State Tables and Graphs 13.4 General Models for Sequential Circuits

3. 32004/05/24Analysis of Clocked Sequential Circuits General Models A sequential circuit Flip-flops Flip-flops Serve as memory for the circuit Combinational logic Combinational logicRealize The input functions for the flip-flops The input functions for the flip-flops The output functions The output functions

4. 42004/05/24Analysis of Clocked Sequential Circuits General Model for Mealy Circuit

5. 52004/05/24Analysis of Clocked Sequential Circuits Minimum Clock Period

6. 62004/05/24Analysis of Clocked Sequential Circuits General Model for Moore Circuit

7. 72004/05/24Analysis of Clocked Sequential Circuits State Table X = 0 X 1 X 2 = 00 X 1 X 2 = 00 X = 1 X 1 X 2 = 01 X 1 X 2 = 01 Z = 0 Z 1 Z 2 = 00 Z = 1 Z 1 Z 2 = 01

8. 82004/05/24Analysis of Clocked Sequential Circuits Homework #6 1.13.2 2.13.3 3.13.4 4.13.5 5.13.6 Paper Submission, due on June 10, 2004. Late submission will not be accepted.