# CSCE 211: Digital Logic Design. Chapter 6: Analysis of Sequential Systems.

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CSCE 211: Digital Logic Design

Chapter 6: Analysis of Sequential Systems

10/22/20133 Sequential System A system that has memory The output will depend not only on the present input but also on the past, on what has happened earlier Will focus on clocked systems (also called synchronous)

10/22/20134 Clock A signal that alternates between 0 and 1 at a regular rate The same clock is normally connected to all flip flops (a clocked binary storage device) The period of the signal is the length of one cycle; the frequency is the inverse of the period In most synchronous systems, change occurs on the transition of the clock signal

10/22/20135 Conceptual View of a Sequential System

10/22/20136 CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times. State: what is stored in memory. It is stored in binary devices, but the information to be stored is not always naturally binary. Timing trace: a set of values for the input and output (and sometimes the state or other variables of the system, as well) at consecutive clock times. A Continuing Example

10/22/20137 State table: shows for each input combination and each state, what the output is and what the next state is, that is, what is to be stored in memory after the next clock. State Tables and Diagrams

10/22/20138 State diagram (or state graph): a graphical representation of the state table. This is an example of Moore model because the output depends only on the state of the system, not the present input. State Tables and Diagrams

10/22/20139 Mealy model: the output depends not only on the present state, but also on the present input. State Tables and Diagrams 1

10/22/201310 P = (S + Q)´ Q = (R + P)´ Latch A binary storage device, composed of two or more gates, with feedback

10/22/201311 Gated Latch When Gate is 0, latch remains unchanged When Gate goes to 1, it behaves like the simpler latch

10/22/201312 Flip Flop A clocked binary storage device that stores either 0 or 1 State of flip flop changes on the transition of the clock Trailing-edge triggered: change takes place when the clock goes from 1 to 0 Leading-edge triggered: change takes place when the clock goes from 0 to 1

10/22/201313 Flip Flop What is stored after the transition depends on the data inputs and might also depend on what was stored in the flip flop prior to the transition Flip flops have one or two outputs State of the flip flop If there is a second output, it is the complement of the state

10/22/201314 D Flip Flop D means Delay Output is the input delayed until the next active clock transition Next state of D flip flop is the value of D before clock transition

10/22/201315 D Flip Flop

10/22/201316 Timing Diagram of D Flip Flop

10/22/201317 Two Flip Flops Connect the output of one flip flop to the input of another flip flop, and clock them simultaneously At a clock transition when the first flip flop q changes, the old value of q is used to compute the behavior of r

10/22/201318 Two Flip Flops

10/22/201319 Flip Flop with Clear and Preset

10/22/201320 Flip Flop with Clear and Preset

10/22/201321 T Flip Flop T means Toggle If input T is 1, the flip flop changes state (i.e. is toggled) If T is 0, the state remains the same

10/22/201322 T Flip Flop

10/22/201323 Timing Diagram of T Flip Flop

10/22/201324 JK Flip Flop JK is not an acronym of anything If J = 0 and K = 0, the flip flop holds the current state If J = 0 and K = 1, the flip flop resets q to 0 If J = 1 and K = 0, the flip flop sets q to 1 If J = 1 and K = 1, the flip flop changes its state

10/22/201325 q* = Jq´ + K´q JK Flip Flop

10/22/201326 Timing Diagram of JK Flip Flop

10/22/201327 Review: Conceptual View of a Sequential System

10/22/201328 D 1 = q 1 q´ 2 + x q´ 1 = q 1 * D 2 = xq 1 = q 2 * z = q´ 2 12 Analysis Example 1

10/22/201329 Analysis Example 1 D 1 = q 1 q´ 2 + x q´ 1 = q 1 * D 2 = xq 1 = q 2 * z = q´ 2

10/22/201330 J A = xK A = xB´ J B = K B = x + A´ z = A + B Analysis Example 2

10/22/201331 Analysis Example 2

10/22/201332 Analysis Example 2

10/22/201333 D 1 = xq 1 + xq 2 D 2 = xq´ 1 q´ 2 z = xq 1 Analysis Example 3

10/22/201334 Analysis Example 3

10/22/201335 Analysis Example 3

10/22/201336 Analysis Example 4 Is this Moore model or Mealy model? Draw timing diagram for input x = 0 1 1 0 1 1 1 1 0

10/22/201337 Analysis Example 4

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