# Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh.

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Unit 11 Latches and Flip-Flops Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

22004/04/18Latches and Flip-flops Outline 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop 11.6J-K Flip-Flop 11.7T Flip-Flop 11.8Flip-Flops with Additional Inputs 11.9Summary

32004/04/18Latches and Flip-flops Introduction Sequential switching circuits The output depends on The output depends on Present input Past sequence of inputs ‘remember’ something about the past history of the inputs ‘remember’ something about the past history of the inputs Two commonly used memory devices in sequential circuits Latches – no clock input Latches – no clock input Flip-flops Flip-flops

42004/04/18Latches and Flip-flops Feedback The output of one of the gates is connected back into the input of another gate in the circuit so as to form a closed loop. The rate at which the circuit oscillates is determined by the propagation delay in the inverter.

52004/04/18Latches and Flip-flops Two Inverters with a Feedback Loop Two stable conditions Often referred to as stable states Often referred to as stable states

62004/04/18Latches and Flip-flops Outline 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop 11.6J-K Flip-Flop 11.7T Flip-Flop 11.8Flip-Flops with Additional Inputs 11.9Summary

72004/04/18Latches and Flip-flops Set-Reset Latch Introduce feedback into a NOR-gate circuit S=R=0 is a stable condition S=R=0 is a stable condition S=1 and R=0 is a stable condition S=1 and R=0 is a stable condition

82004/04/18Latches and Flip-flops Set-Reset Latch

92004/04/18Latches and Flip-flops Set-Reset Latch This circuit is said to have memory because its output depends not only on the present inputs, but also on the past sequence of inputs.

102004/04/18Latches and Flip-flops Set-Reset Latch R = S = 1 is not allowed The outputs P and Q are always complements, that is, P = Q’. The outputs P and Q are always complements, that is, P = Q’. The circuit is in cross-coupled form. The circuit is in cross-coupled form.

112004/04/18Latches and Flip-flops Set-Reset Latch An input S = 1 sets the output to Q = 1 An input R = 1 resets the output to Q = 0 R and S cannot be 1 simultaneously

122004/04/18Latches and Flip-flops Improper S-R Latch Operation The latch may continue to oscillate if the gate delays are equal.

132004/04/18Latches and Flip-flops Timing Diagram

142004/04/18Latches and Flip-flops S-R Latch Operation S(t)R(t)Q(t) Q(t+  ) 0000 0011 0100 0110 1001 1011 110- 111-

152004/04/18Latches and Flip-flops Map and Equation of the Latch Next-state equation, or characteristic equation Q + = S + R’ Q (SR=0) Q + = S + R’ Q (SR=0)

162004/04/18Latches and Flip-flops S-R Latch Applications Components in more complex latches and flip- flops Debouncing switching

172004/04/18Latches and Flip-flops S-R Latch An alternative form of the S-R latch uses NAND gates

182004/04/18Latches and Flip-flops S-R Latch S = 0 will set Q to 1 R = 0 will set Q to 0 S = R = 0 is not allowed SRQ Q+Q+Q+Q+ 1100 1111 1000 1010 0101 0111 000- 001-

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